SH7757 has SPI module. This patch supports it.
Signed-off-by: Yoshihiro Shimoda
---
about v2:
- add prefix of "SH_" to some defines.
- modify spi_cs_is_valid()
drivers/spi/Makefile |1 +
drivers/spi/sh_spi.c | 301 ++
2 files changed, 302 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/sh_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e34a124..d582fbb 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
+COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
new file mode 100644
index 000..633450c
--- /dev/null
+++ b/drivers/spi/sh_spi.c
@@ -0,0 +1,301 @@
+/*
+ * SH SPI driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+#define SH_SPI_TBR 0x00
+#define SH_SPI_RBR 0x00
+#define SH_SPI_CR1 0x08
+#define SH_SPI_CR2 0x10
+#define SH_SPI_CR3 0x18
+#define SH_SPI_CR4 0x20
+
+/* CR1 */
+#define SH_SPI_TBE 0x80
+#define SH_SPI_TBF 0x40
+#define SH_SPI_RBE 0x20
+#define SH_SPI_RBF 0x10
+#define SH_SPI_PFONRD 0x08
+#define SH_SPI_SSDB0x04
+#define SH_SPI_SSD 0x02
+#define SH_SPI_SSA 0x01
+
+/* CR2 */
+#define SH_SPI_RSTF0x80
+#define SH_SPI_LOOPBK 0x40
+#define SH_SPI_CPOL0x20
+#define SH_SPI_CPHA0x10
+#define SH_SPI_L1M00x08
+
+/* CR3 */
+#define SH_SPI_MAX_BYTE0xFF
+
+/* CR4 */
+#define SH_SPI_TBEI0x80
+#define SH_SPI_TBFI0x40
+#define SH_SPI_RBEI0x20
+#define SH_SPI_RBFI0x10
+#define SH_SPI_WPABRT 0x04
+#define SH_SPI_SSS 0x01
+
+#define SH_SPI_FIFO_SIZE 32
+
+static void sh_spi_write(unsigned long data, unsigned long offset)
+{
+ writel(data, CONFIG_SH_SPI_BASE + offset);
+}
+
+static unsigned long sh_spi_read(unsigned long offset)
+{
+ return readl(CONFIG_SH_SPI_BASE + offset);
+}
+
+static void sh_spi_set_bit(unsigned long val, unsigned long offset)
+{
+ unsigned long tmp;
+
+ tmp = sh_spi_read(offset);
+ tmp |= val;
+ sh_spi_write(tmp, offset);
+}
+
+static void sh_spi_clear_bit(unsigned long val, unsigned long offset)
+{
+ unsigned long tmp;
+
+ tmp = sh_spi_read(offset);
+ tmp &= ~val;
+ sh_spi_write(tmp, offset);
+}
+
+static void clear_fifo(void)
+{
+ sh_spi_set_bit(SH_SPI_RSTF, SH_SPI_CR2);
+ sh_spi_clear_bit(SH_SPI_RSTF, SH_SPI_CR2);
+}
+
+static int recvbuf_wait(void)
+{
+ while (sh_spi_read(SH_SPI_CR1) & SH_SPI_RBE) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+ return 0;
+}
+
+static int write_fifo_full_wait(void)
+{
+ while (sh_spi_read(SH_SPI_CR1) & SH_SPI_TBF) {
+ udelay(10);
+ if (ctrlc())
+ return 1;
+ }
+ return 0;
+}
+
+static int write_fifo_empty_wait(void)
+{
+ while (!(sh_spi_read(SH_SPI_CR1) & SH_SPI_TBE)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+ return 0;
+}
+
+void spi_init(void)
+{
+
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct spi_slave *slave;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ slave = malloc(sizeof(struct spi_slave));
+ if (!slave)
+ return NULL;
+
+ slave->bus = bus;
+ slave->cs = cs;
+
+ /* SPI sycle stop */
+ sh_spi_write(0xfe, SH_SPI_CR1);
+ /* CR1 init */
+ sh_spi_write(0x00, SH_SPI_CR1);
+ /* CR3 init */
+ sh_spi_write(0x00, SH_SPI_CR3);
+
+ clear_fifo();
+
+ /* 1/8 clock */
+ sh_spi_write(sh_spi_read(SH_SPI_CR2) | 0x07, SH_SPI_CR2);
+ udelay(10);
+
+ return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_sla
