[U-Boot] [PATCH v2 01/12] riscv: cpu: Add nx25 to support RISC-V

2017-12-25 Thread Andes 
From: Rick Chen 

Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch

Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.

Detail verification message please see doc/README.ae250.

Signed-off-by: Rick Chen 
Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
Cc: Padmarao Begari 
---
 arch/riscv/cpu/nx25/Makefile   |  10 ++
 arch/riscv/cpu/nx25/cpu.c  |  33 +
 arch/riscv/cpu/nx25/start.S| 291 +
 arch/riscv/cpu/nx25/u-boot.lds |  69 ++
 4 files changed, 403 insertions(+)
 create mode 100644 arch/riscv/cpu/nx25/Makefile
 create mode 100644 arch/riscv/cpu/nx25/cpu.c
 create mode 100644 arch/riscv/cpu/nx25/start.S
 create mode 100644 arch/riscv/cpu/nx25/u-boot.lds

diff --git a/arch/riscv/cpu/nx25/Makefile b/arch/riscv/cpu/nx25/Makefile
new file mode 100644
index 000..5fcf100
--- /dev/null
+++ b/arch/riscv/cpu/nx25/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y= start.o
+
+obj-y  := cpu.o
diff --git a/arch/riscv/cpu/nx25/cpu.c b/arch/riscv/cpu/nx25/cpu.c
new file mode 100644
index 000..5478f4f
--- /dev/null
+++ b/arch/riscv/cpu/nx25/cpu.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/* CPU specific code */
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+   disable_interrupts();
+
+   /* turn off I/D-cache */
+
+   return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   disable_interrupts();
+   panic("nx25-ae250 wdt not support yet.\n");
+}
diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S
new file mode 100644
index 000..6a07663
--- /dev/null
+++ b/arch/riscv/cpu/nx25/start.S
@@ -0,0 +1,291 @@
+/*
+ * Startup Code for RISC-V Core
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari 
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_32BIT
+#define LREG   lw
+#define SREG   sw
+#define REGBYTES   4
+#define RELOC_TYPE R_RISCV_32
+#define SYM_INDEX  0x8
+#define SYM_SIZE   0x10
+#else
+#define LREG   ld
+#define SREG   sd
+#define REGBYTES   8
+#define RELOC_TYPE R_RISCV_64
+#define SYM_INDEX  0x20
+#define SYM_SIZE   0x18
+#endif
+
+.section  .text
+.globl _start
+_start:
+   j handle_reset
+
+nmi_vector:
+   j nmi_vector
+
+trap_vector:
+   j trap_entry
+
+.global trap_entry
+handle_reset:
+   la t0, trap_entry
+   csrw mtvec, t0
+   csrwi mstatus, 0
+   csrwi mie, 0
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+   jal cpu_init_crit   /* Do CPU critical regs init */
+#endif
+
+/*
+ * Set stackpointer in internal/ex RAM to call board_init_f
+ */
+call_board_init_f:
+   li  t0, -16
+   li  t1, CONFIG_SYS_INIT_SP_ADDR
+   and sp, t1, t0  /* force 16 byte alignment */
+
+#ifdef CONFIG_DEBUG_UART
+   jal debug_uart_init
+#endif
+
+call_board_init_f_0:
+   mv  a0, sp
+   jal board_init_f_alloc_reserve
+   mv  sp, a0
+   jal board_init_f_init_reserve
+
+   mv  a0, zero/* a0 <-- boot_flags = 0 */
+   la t5, board_init_f
+   jr t5   /* jump to board_init_f() */
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl relocate_code
+relocate_code:
+   mv  s2, a0  /* save addr_sp */
+   mv  s3, a1  /* save addr of gd */
+   mv  s4, a2  /* save addr of destination */
+
+/*
+ *Set up the stack
+ */
+stack_setup:
+   mv sp, s2
+   la t0, _start
+   sub t6, s4, t0  /* t6 <- relocation offset */
+   beq t0, s4, clear_bss   /* skip relocation */
+
+   mv t1, s4   /* t1 <- scratch for copy_loop */
+   la t3, __bss_start
+   sub t3, t3, t0  /* t3 <- __bss_start_ofs */
+   add t2, t0, t3  /* t2 <- source end address */
+
+copy_loop:
+   LREG t5, 0(t0)
+   addi t0, t0, REGBYTES
+   SREG t5, 0(t1)
+   addi t1, t1, REGBYTES
+   blt t0, t2, copy_loop
+
+/*
+

Re: [U-Boot] [PATCH v2 01/12] riscv: cpu: Add nx25 to support RISC-V

2018-01-08 Thread 陳建志 
Hi Tom

How about the Andes NX25 cpu for RISC-V arch patchsets [PATCH v2 x/12]
reviewing status ?
Is everything ok ?

Rick

2017-12-26 13:55 GMT+08:00 Andes :
> From: Rick Chen 
>
> Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch
>
> Verifications:
> 1. startup and relocation ok.
> 2. boot from rom or ram both ok.
> 2. timer driver ok.
> 3. uart driver ok
> 4. mmc driver ok
> 5. spi driver ok.
> 6. 32/64 bit both ok.
>
> Detail verification message please see doc/README.ae250.
>
> Signed-off-by: Rick Chen 
> Signed-off-by: Rick Chen 
> Signed-off-by: Greentime Hu 
> Cc: Padmarao Begari 
> ---
>  arch/riscv/cpu/nx25/Makefile   |  10 ++
>  arch/riscv/cpu/nx25/cpu.c  |  33 +
>  arch/riscv/cpu/nx25/start.S| 291 
> +
>  arch/riscv/cpu/nx25/u-boot.lds |  69 ++
>  4 files changed, 403 insertions(+)
>  create mode 100644 arch/riscv/cpu/nx25/Makefile
>  create mode 100644 arch/riscv/cpu/nx25/cpu.c
>  create mode 100644 arch/riscv/cpu/nx25/start.S
>  create mode 100644 arch/riscv/cpu/nx25/u-boot.lds
>
> diff --git a/arch/riscv/cpu/nx25/Makefile b/arch/riscv/cpu/nx25/Makefile
> new file mode 100644
> index 000..5fcf100
> --- /dev/null
> +++ b/arch/riscv/cpu/nx25/Makefile
> @@ -0,0 +1,10 @@
> +#
> +# Copyright (C) 2017 Andes Technology Corporation
> +# Rick Chen, Andes Technology Corporation 
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +extra-y= start.o
> +
> +obj-y  := cpu.o
> diff --git a/arch/riscv/cpu/nx25/cpu.c b/arch/riscv/cpu/nx25/cpu.c
> new file mode 100644
> index 000..5478f4f
> --- /dev/null
> +++ b/arch/riscv/cpu/nx25/cpu.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (C) 2017 Andes Technology Corporation
> + * Rick Chen, Andes Technology Corporation 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +/* CPU specific code */
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/*
> + * cleanup_before_linux() is called just before we call linux
> + * it prepares the processor for linux
> + *
> + * we disable interrupt and caches.
> + */
> +int cleanup_before_linux(void)
> +{
> +   disable_interrupts();
> +
> +   /* turn off I/D-cache */
> +
> +   return 0;
> +}
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> +   disable_interrupts();
> +   panic("nx25-ae250 wdt not support yet.\n");
> +}
> diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S
> new file mode 100644
> index 000..6a07663
> --- /dev/null
> +++ b/arch/riscv/cpu/nx25/start.S
> @@ -0,0 +1,291 @@
> +/*
> + * Startup Code for RISC-V Core
> + *
> + * Copyright (c) 2017 Microsemi Corporation.
> + * Copyright (c) 2017 Padmarao Begari 
> + *
> + * Copyright (C) 2017 Andes Technology Corporation
> + * Rick Chen, Andes Technology Corporation 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#ifdef CONFIG_32BIT
> +#define LREG   lw
> +#define SREG   sw
> +#define REGBYTES   4
> +#define RELOC_TYPE R_RISCV_32
> +#define SYM_INDEX  0x8
> +#define SYM_SIZE   0x10
> +#else
> +#define LREG   ld
> +#define SREG   sd
> +#define REGBYTES   8
> +#define RELOC_TYPE R_RISCV_64
> +#define SYM_INDEX  0x20
> +#define SYM_SIZE   0x18
> +#endif
> +
> +.section  .text
> +.globl _start
> +_start:
> +   j handle_reset
> +
> +nmi_vector:
> +   j nmi_vector
> +
> +trap_vector:
> +   j trap_entry
> +
> +.global trap_entry
> +handle_reset:
> +   la t0, trap_entry
> +   csrw mtvec, t0
> +   csrwi mstatus, 0
> +   csrwi mie, 0
> +
> +/*
> + * Do CPU critical regs init only at reboot,
> + * not when booting from ram
> + */
> +#ifdef CONFIG_INIT_CRITICAL
> +   jal cpu_init_crit   /* Do CPU critical regs init */
> +#endif
> +
> +/*
> + * Set stackpointer in internal/ex RAM to call board_init_f
> + */
> +call_board_init_f:
> +   li  t0, -16
> +   li  t1, CONFIG_SYS_INIT_SP_ADDR
> +   and sp, t1, t0  /* force 16 byte alignment */
> +
> +#ifdef CONFIG_DEBUG_UART
> +   jal debug_uart_init
> +#endif
> +
> +call_board_init_f_0:
> +   mv  a0, sp
> +   jal board_init_f_alloc_reserve
> +   mv  sp, a0
> +   jal board_init_f_init_reserve
> +
> +   mv  a0, zero/* a0 <-- boot_flags = 0 */
> +   la t5, board_init_f
> +   jr t5   /* jump to board_init_f() */
> +
> +/*
> + * void relocate_code (addr_sp, gd, addr_moni)
> + *
> + * This "function" does not return, instead it continues in RAM
> + * after relocating the monitor code.
> + *
> + */
> +.globl relocate_code
> +relocate_code:
> +   mv  s2, a0  /* save addr_sp */
> +   mv  s3, a1  /* save addr of gd */
> +   mv  s4, a2  /* save addr of destination */
> +
> +/*
> + *Se

Re: [U-Boot] [PATCH v2 01/12] riscv: cpu: Add nx25 to support RISC-V

2018-01-09 Thread Tom Rini 
On Tue, Jan 09, 2018 at 01:47:23PM +0800, 陳建志 wrote:
> Hi Tom
> 
> How about the Andes NX25 cpu for RISC-V arch patchsets [PATCH v2 x/12]
> reviewing status ?
> Is everything ok ?

Yes, I think everything is OK.  Can you please also include an update to
.travis.yml that gets the architecture to be built during CI?  Thanks!

-- 
Tom


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