Re: [U-Boot] [PATCH v2 02/18] gpio: Add support for Qualcomm gpio controller
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi All,
Sorry for long delay :)
On 16.02.2016 16:59, Simon Glass wrote:
> Hi,
>
> On 9 February 2016 at 14:25, Jagan Teki wrote:
>> On 8 February 2016 at 02:27, Mateusz Kulikowski
>> wrote:
[...]
>>> +
>>> +Required properties:
>>> +- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
>>> +- reg : Physical base address and length of the controller's registers.
>>> + This controller is called "Top Level Mode Multiplexing" in
>>> + Qualcomm documentation.
>>> +- #gpio-cells : Should be one (pin number).
>>> +- gpio-controller : Marks the device node as a GPIO controller.
>>> +- gpio-count: Number of GPIO pins.
>>> +- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
>>> +
>>> +Example:
>>> +
>>> +soc_gpios: pinctrl@100 {
>>> + compatible = "qcom,msm8916-pinctrl";
>>
>> Can't this driver goes into pinctrl (I mean gpio handling pincontrol),
>> because Linux handle these gpio msm8916-pinctrl through pinctrl
>> subsystem as per as I know, let me know in case if I miss anything
>> here.
>
> I think Mateusz is planning to add this later. It would be good to get
> this in as a starting point for this platform.
It was exactly my plan. Is it OK with you Jagan?
Regards,
Mateusz
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Re: [U-Boot] [PATCH v2 02/18] gpio: Add support for Qualcomm gpio controller
Hi,
On 9 February 2016 at 14:25, Jagan Teki wrote:
> On 8 February 2016 at 02:27, Mateusz Kulikowski
> wrote:
>> Add support for gpio controllers on Qualcomm Snapdragon devices.
>> This devices are usually called Top Level Mode Multiplexing in
>> Qualcomm documentation.
>>
>> Signed-off-by: Mateusz Kulikowski
>> Reviewed-by: Simon Glass
>> Tested-by: Simon Glass
>> ---
>>
>> Changes in v3: None
>> Changes in v2:
>> - Reordered includes (again)
>> - Added newlines between returns
>> - Fixed error handling in msm_gpio_probe
>> - Added reviewed-by
>>
>> Changes in v1:
>> - Added dt binding documentation
>> - Added help to KConfig
>> - Use clrsetbits() to switch direction
>> - Fixed include order
>> - Added #defines for registers/register fields
>> - Added secondary compatible string
>>
>> doc/device-tree-bindings/gpio/gpio-msm.txt | 22 +
>> drivers/gpio/Kconfig | 14 +++
>> drivers/gpio/Makefile | 1 +
>> drivers/gpio/msm_gpio.c| 135
>> +
>> 4 files changed, 172 insertions(+)
>> create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt
>> create mode 100644 drivers/gpio/msm_gpio.c
>>
>> diff --git a/doc/device-tree-bindings/gpio/gpio-msm.txt
>> b/doc/device-tree-bindings/gpio/gpio-msm.txt
>> new file mode 100644
>> index 000..966ce0a
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/gpio/gpio-msm.txt
>> @@ -0,0 +1,22 @@
>> +Qualcomm Snapdragon GPIO controller
>> +
>> +Required properties:
>> +- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
>> +- reg : Physical base address and length of the controller's registers.
>> + This controller is called "Top Level Mode Multiplexing" in
>> + Qualcomm documentation.
>> +- #gpio-cells : Should be one (pin number).
>> +- gpio-controller : Marks the device node as a GPIO controller.
>> +- gpio-count: Number of GPIO pins.
>> +- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
>> +
>> +Example:
>> +
>> +soc_gpios: pinctrl@100 {
>> + compatible = "qcom,msm8916-pinctrl";
>
> Can't this driver goes into pinctrl (I mean gpio handling pincontrol),
> because Linux handle these gpio msm8916-pinctrl through pinctrl
> subsystem as per as I know, let me know in case if I miss anything
> here.
I think Mateusz is planning to add this later. It would be good to get
this in as a starting point for this platform.
Regards,
Simon
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Re: [U-Boot] [PATCH v2 02/18] gpio: Add support for Qualcomm gpio controller
On 8 February 2016 at 02:27, Mateusz Kulikowski
wrote:
> Add support for gpio controllers on Qualcomm Snapdragon devices.
> This devices are usually called Top Level Mode Multiplexing in
> Qualcomm documentation.
>
> Signed-off-by: Mateusz Kulikowski
> Reviewed-by: Simon Glass
> Tested-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2:
> - Reordered includes (again)
> - Added newlines between returns
> - Fixed error handling in msm_gpio_probe
> - Added reviewed-by
>
> Changes in v1:
> - Added dt binding documentation
> - Added help to KConfig
> - Use clrsetbits() to switch direction
> - Fixed include order
> - Added #defines for registers/register fields
> - Added secondary compatible string
>
> doc/device-tree-bindings/gpio/gpio-msm.txt | 22 +
> drivers/gpio/Kconfig | 14 +++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/msm_gpio.c| 135
> +
> 4 files changed, 172 insertions(+)
> create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt
> create mode 100644 drivers/gpio/msm_gpio.c
>
> diff --git a/doc/device-tree-bindings/gpio/gpio-msm.txt
> b/doc/device-tree-bindings/gpio/gpio-msm.txt
> new file mode 100644
> index 000..966ce0a
> --- /dev/null
> +++ b/doc/device-tree-bindings/gpio/gpio-msm.txt
> @@ -0,0 +1,22 @@
> +Qualcomm Snapdragon GPIO controller
> +
> +Required properties:
> +- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
> +- reg : Physical base address and length of the controller's registers.
> + This controller is called "Top Level Mode Multiplexing" in
> + Qualcomm documentation.
> +- #gpio-cells : Should be one (pin number).
> +- gpio-controller : Marks the device node as a GPIO controller.
> +- gpio-count: Number of GPIO pins.
> +- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
> +
> +Example:
> +
> +soc_gpios: pinctrl@100 {
> + compatible = "qcom,msm8916-pinctrl";
Can't this driver goes into pinctrl (I mean gpio handling pincontrol),
because Linux handle these gpio msm8916-pinctrl through pinctrl
subsystem as per as I know, let me know in case if I miss anything
here.
> + reg = <0x100 0x30>;
> + gpio-controller;
> + gpio-count = <122>;
> + gpio-bank-name="soc";
> + #gpio-cells = <1>;
> +};
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 845dc72..a5e8182 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -46,6 +46,20 @@ config LPC32XX_GPIO
> help
> Support for the LPC32XX GPIO driver.
>
> +config MSM_GPIO
> + bool "Qualcomm GPIO driver"
> + depends on DM_GPIO
> + default n
> + help
> + Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
> + This controller have single bank (default name "soc"), every
> + gpio has it's own set of registers.
> + Only simple GPIO operations are supported (get/set, change of
> + direction and checking pin function).
> + Supported devices:
> + - APQ8016
> + - MSM8916
> +
> config ROCKCHIP_GPIO
> bool "Rockchip GPIO driver"
> depends on DM_GPIO
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 845a6d4..6083c4a 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -47,3 +47,4 @@ obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
> obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
> obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
> obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
> +obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
> diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
> new file mode 100644
> index 000..950f309
> --- /dev/null
> +++ b/drivers/gpio/msm_gpio.c
> @@ -0,0 +1,135 @@
> +/*
> + * Qualcomm GPIO driver
> + *
> + * (C) Copyright 2015 Mateusz Kulikowski
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* Register offsets */
> +#define GPIO_CONFIG_OFF(no) ((no) * 0x1000)
> +#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)
> +
> +/* OE */
> +#define GPIO_OE_DISABLE (0x0 << 9)
> +#define GPIO_OE_ENABLE (0x1 << 9)
> +#define GPIO_OE_MASK (0x1 << 9)
> +
> +/* GPIO_IN_OUT register shifts. */
> +#define GPIO_IN 0
> +#define GPIO_OUT 1
> +
> +struct msm_gpio_bank {
> + phys_addr_t base;
> +};
> +
> +static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
> +{
> + struct msm_gpio_bank *priv = dev_get_priv(dev);
> + phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
> +
> + /* Disable OE bit */
> + clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
> +
> + return 0;
> +}
> +
> +static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
> +{
> + struct msm_gpio_bank *priv
[U-Boot] [PATCH v2 02/18] gpio: Add support for Qualcomm gpio controller
Add support for gpio controllers on Qualcomm Snapdragon devices.
This devices are usually called Top Level Mode Multiplexing in
Qualcomm documentation.
Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Reordered includes (again)
- Added newlines between returns
- Fixed error handling in msm_gpio_probe
- Added reviewed-by
Changes in v1:
- Added dt binding documentation
- Added help to KConfig
- Use clrsetbits() to switch direction
- Fixed include order
- Added #defines for registers/register fields
- Added secondary compatible string
doc/device-tree-bindings/gpio/gpio-msm.txt | 22 +
drivers/gpio/Kconfig | 14 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/msm_gpio.c| 135 +
4 files changed, 172 insertions(+)
create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt
create mode 100644 drivers/gpio/msm_gpio.c
diff --git a/doc/device-tree-bindings/gpio/gpio-msm.txt
b/doc/device-tree-bindings/gpio/gpio-msm.txt
new file mode 100644
index 000..966ce0a
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/gpio-msm.txt
@@ -0,0 +1,22 @@
+Qualcomm Snapdragon GPIO controller
+
+Required properties:
+- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
+- reg : Physical base address and length of the controller's registers.
+ This controller is called "Top Level Mode Multiplexing" in
+ Qualcomm documentation.
+- #gpio-cells : Should be one (pin number).
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
+
+Example:
+
+soc_gpios: pinctrl@100 {
+ compatible = "qcom,msm8916-pinctrl";
+ reg = <0x100 0x30>;
+ gpio-controller;
+ gpio-count = <122>;
+ gpio-bank-name="soc";
+ #gpio-cells = <1>;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 845dc72..a5e8182 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -46,6 +46,20 @@ config LPC32XX_GPIO
help
Support for the LPC32XX GPIO driver.
+config MSM_GPIO
+ bool "Qualcomm GPIO driver"
+ depends on DM_GPIO
+ default n
+ help
+ Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
+ This controller have single bank (default name "soc"), every
+ gpio has it's own set of registers.
+ Only simple GPIO operations are supported (get/set, change of
+ direction and checking pin function).
+ Supported devices:
+ - APQ8016
+ - MSM8916
+
config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 845a6d4..6083c4a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
+obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
new file mode 100644
index 000..950f309
--- /dev/null
+++ b/drivers/gpio/msm_gpio.c
@@ -0,0 +1,135 @@
+/*
+ * Qualcomm GPIO driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offsets */
+#define GPIO_CONFIG_OFF(no) ((no) * 0x1000)
+#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)
+
+/* OE */
+#define GPIO_OE_DISABLE (0x0 << 9)
+#define GPIO_OE_ENABLE (0x1 << 9)
+#define GPIO_OE_MASK (0x1 << 9)
+
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN 0
+#define GPIO_OUT 1
+
+struct msm_gpio_bank {
+ phys_addr_t base;
+};
+
+static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+ phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+ /* Disable OE bit */
+ clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
+
+ return 0;
+}
+
+static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+ value = !!value;
+ /* set value */
+ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+
+ return 0;
+}
+
+static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
+int value)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+ phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+ value = !!value;
+ /* set value */
+ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+ /* switch directi
Re: [U-Boot] [PATCH v2 02/18] gpio: Add support for Qualcomm gpio controller
On 24 January 2016 at 13:52, Mateusz Kulikowski wrote: > Add support for gpio controllers on Qualcomm Snapdragon devices. > This devices are usually called Top Level Mode Multiplexing in > Qualcomm documentation. > > Signed-off-by: Mateusz Kulikowski > Reviewed-by: Simon Glass > --- > > Changes in v2: > - Reordered includes (again) > - Added newlines between returns > - Fixed error handling in msm_gpio_probe > - Added reviewed-by > > Changes in v1: > - Added dt binding documentation > - Added help to KConfig > - Use clrsetbits() to switch direction > - Fixed include order > - Added #defines for registers/register fields > - Added secondary compatible string > > doc/device-tree-bindings/gpio/gpio-msm.txt | 22 + > drivers/gpio/Kconfig | 14 +++ > drivers/gpio/Makefile | 2 +- > drivers/gpio/msm_gpio.c| 135 > + > 4 files changed, 172 insertions(+), 1 deletion(-) > create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt > create mode 100644 drivers/gpio/msm_gpio.c Tested-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/18] gpio: Add support for Qualcomm gpio controller
Add support for gpio controllers on Qualcomm Snapdragon devices.
This devices are usually called Top Level Mode Multiplexing in
Qualcomm documentation.
Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
---
Changes in v2:
- Reordered includes (again)
- Added newlines between returns
- Fixed error handling in msm_gpio_probe
- Added reviewed-by
Changes in v1:
- Added dt binding documentation
- Added help to KConfig
- Use clrsetbits() to switch direction
- Fixed include order
- Added #defines for registers/register fields
- Added secondary compatible string
doc/device-tree-bindings/gpio/gpio-msm.txt | 22 +
drivers/gpio/Kconfig | 14 +++
drivers/gpio/Makefile | 2 +-
drivers/gpio/msm_gpio.c| 135 +
4 files changed, 172 insertions(+), 1 deletion(-)
create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt
create mode 100644 drivers/gpio/msm_gpio.c
diff --git a/doc/device-tree-bindings/gpio/gpio-msm.txt
b/doc/device-tree-bindings/gpio/gpio-msm.txt
new file mode 100644
index 000..966ce0a
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/gpio-msm.txt
@@ -0,0 +1,22 @@
+Qualcomm Snapdragon GPIO controller
+
+Required properties:
+- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
+- reg : Physical base address and length of the controller's registers.
+ This controller is called "Top Level Mode Multiplexing" in
+ Qualcomm documentation.
+- #gpio-cells : Should be one (pin number).
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
+
+Example:
+
+soc_gpios: pinctrl@100 {
+ compatible = "qcom,msm8916-pinctrl";
+ reg = <0x100 0x30>;
+ gpio-controller;
+ gpio-count = <122>;
+ gpio-bank-name="soc";
+ #gpio-cells = <1>;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e60e9fd..3d112b9 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -46,6 +46,20 @@ config LPC32XX_GPIO
help
Support for the LPC32XX GPIO driver.
+config MSM_GPIO
+ bool "Qualcomm GPIO driver"
+ depends on DM_GPIO
+ default n
+ help
+ Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
+ This controller have single bank (default name "soc"), every
+ gpio has it's own set of registers.
+ Only simple GPIO operations are supported (get/set, change of
+ direction and checking pin function).
+ Supported devices:
+ - APQ8016
+ - MSM8916
+
config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb4fd25..9520b1e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
-
+obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
new file mode 100644
index 000..950f309
--- /dev/null
+++ b/drivers/gpio/msm_gpio.c
@@ -0,0 +1,135 @@
+/*
+ * Qualcomm GPIO driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offsets */
+#define GPIO_CONFIG_OFF(no) ((no) * 0x1000)
+#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)
+
+/* OE */
+#define GPIO_OE_DISABLE (0x0 << 9)
+#define GPIO_OE_ENABLE (0x1 << 9)
+#define GPIO_OE_MASK (0x1 << 9)
+
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN 0
+#define GPIO_OUT 1
+
+struct msm_gpio_bank {
+ phys_addr_t base;
+};
+
+static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+ phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+ /* Disable OE bit */
+ clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
+
+ return 0;
+}
+
+static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+ value = !!value;
+ /* set value */
+ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+
+ return 0;
+}
+
+static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
+int value)
+{
+ struct msm_gpio_bank *priv = dev_get_priv(dev);
+ phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+ value = !!value;
+ /* set value */
+ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+ /* switch direction */
+ clrsetbits_l
