Re: [U-Boot] [PATCH v2 03/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,   wrote:
> From: Chin Liang See 
>
> Add Reset Manager driver support for Stratix SoC
>
> Signed-off-by: Chin Liang See 
> ---
>  arch/arm/mach-socfpga/Makefile |   1 +
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
>  .../include/mach/reset_manager_arria10.h   |   8 +-
>  .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 
>  arch/arm/mach-socfpga/reset_manager.c  |  41 +++
>  arch/arm/mach-socfpga/reset_manager_arria10.c  |  67 +++-
>  arch/arm/mach-socfpga/reset_manager_gen5.c |  33 --
>  arch/arm/mach-socfpga/reset_manager_s10.c  | 118 
> +
>  include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97 +
>  9 files changed, 395 insertions(+), 88 deletions(-)

Yikes! Can you find a way to split this patch up? Looks like you're
adding support
for Stratix10, but you're also messing with gen5 and arria10 stuff,
it's a bit hard to
review.

Thanks,
Dinh
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[U-Boot] [PATCH v2 03/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/Makefile |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h   |   8 +-
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 
 arch/arm/mach-socfpga/reset_manager.c  |  41 +++
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  67 +++-
 arch/arm/mach-socfpga/reset_manager_gen5.c |  33 --
 arch/arm/mach-socfpga/reset_manager_s10.c  | 118 +
 include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97 +
 9 files changed, 395 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e5f9dd7..f10b05c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += reset_manager_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6591745..577fcce 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include 
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index b6d7f4f..e521839 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -28,10 +28,10 @@ struct socfpga_reset_manager {
u32 hdskreq;
u32 hdskack;
u32 counts;
-   u32 mpumodrst;
-   u32 per0modrst;
-   u32 per1modrst;
-   u32 brgmodrst;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;
+   u32 per2_mod_reset;
+   u32 brg_mod_reset;
u32 sysmodrst;
u32 coldmodrst;
u32 nrstmodrst;
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
new file mode 100644
index 000..07ada59
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_RESET_MANAGER_S10_
+#define_RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+   u32 status;
+   u32 mpu_rst_stat;
+   u32 misc_stat;
+   u32 padding1;
+   u32 hdsk_en;
+   u32 hdsk_req;
+   u32 hdsk_ack;
+   u32 hdsk_stall;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in S10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
+   u32 brg_mod_reset;
+   u32 padding2;
+   u32 cold_mod_reset;
+   u32 padding3;
+   u32 dbg_mod_reset;
+   u32 tap_mod_reset;
+   u32 padding4;
+   u32 padding5;
+   u32 brg_warm_mask;
+   u32 padding6[3];
+   u32 tst_stat;
+   u32 padding7;
+   u32 hdsk_timeout;
+   u32 mpul2flushtimeout;
+   u32 dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0 0
+#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK   0X0040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET 8
+#define RSTMGR_BANK_MASK   0x7
+#define RSTMGR_RESET_OFFSET0
+#define RSTMGR_RESET_MASK  0x1f
+#define RSTMGR_DEFINE(_bank, _offset)  \
+   ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)   \
+   (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset)