Re: [U-Boot] [PATCH v2 03/21] vybrid: ddr: Extend vf610-pinfunc.h with DDR pads definitions

[Stefan Agner]

On 20.01.2019 14:34, Lukasz Majewski wrote:
> This patch provides definitions necessary for VF610 DDR pad configurations.
> 
> Signed-off-by: Lukasz Majewski 

Reviewed-by: Stefan Agner 

--
Stefan

> ---
> 
> Changes in v2: None
> 
>  arch/arm/dts/vf610-pinfunc.h | 50 
> 
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h
> index fcad7132c8..24d7126756 100644
> --- a/arch/arm/dts/vf610-pinfunc.h
> +++ b/arch/arm/dts/vf610-pinfunc.h
> @@ -807,4 +807,54 @@
>  #define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0
>  #define VF610_PAD_PTA7__VIU_PIX_CLK  0x218 0x3AC ALT1 0x1
>  
> +#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A15__DDR_A_15  0x220 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A14__DDR_A_14  0x224 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A13__DDR_A_13  0x228 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A12__DDR_A_12  0x22c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A11__DDR_A_11  0x230 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A10__DDR_A_10  0x234 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A9__DDR_A_90x238 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A8__DDR_A_80x23c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A7__DDR_A_70x240 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A6__DDR_A_60x244 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A5__DDR_A_50x248 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A4__DDR_A_40x24c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A3__DDR_A_30x250 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A2__DDR_A_20x254 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A1__DDR_A_10x258 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_A0__DDR_A_00x25c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_BA2__DDR_BA_2  0x260 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_BA1__DDR_BA_1  0x264 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_BA0__DDR_BA_0  0x268 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D15__DDR_D_15  0x27c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D14__DDR_D_14  0x280 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D13__DDR_D_13  0x284 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D12__DDR_D_12  0x288 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D11__DDR_D_11  0x28c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D10__DDR_D_10  0x290 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D9__DDR_D_90x294 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D8__DDR_D_80x298 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D7__DDR_D_70x29c 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D6__DDR_D_60x2a0 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D5__DDR_D_50x2a4 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D4__DDR_D_40x2a8 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D3__DDR_D_30x2ac 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D2__DDR_D_20x2b0 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D1__DDR_D_10x2b4 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_D0__DDR_D_00x2b8 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_DQM1__DDR_DQM_10x2bc 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_DQM0__DDR_DQM_00x2c0 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_DQS1__DDR_DQS_10x2c4 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_DQS0__DDR_DQS_00x2c8 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_WE__DDR_WE_B   0x2d0 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_ODT1__DDR_ODT_00x2d4 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_ODT0__DDR_ODT_10x2d8 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0
> +#define VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 0x2e0 0x000 ALT0 0x0
>  #endif
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[U-Boot] [PATCH v2 03/21] vybrid: ddr: Extend vf610-pinfunc.h with DDR pads definitions

[Lukasz Majewski]

This patch provides definitions necessary for VF610 DDR pad configurations.

Signed-off-by: Lukasz Majewski 
---

Changes in v2: None

 arch/arm/dts/vf610-pinfunc.h | 50 
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h
index fcad7132c8..24d7126756 100644
--- a/arch/arm/dts/vf610-pinfunc.h
+++ b/arch/arm/dts/vf610-pinfunc.h
@@ -807,4 +807,54 @@
 #define VF610_PAD_PTA7__GPIO_134   0x218 0x000 ALT0 0x0
 #define VF610_PAD_PTA7__VIU_PIX_CLK0x218 0x3AC ALT1 0x1
 
+#define VF610_PAD_DDR_RESETB   0x21c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A15__DDR_A_150x220 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A14__DDR_A_140x224 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A13__DDR_A_130x228 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A12__DDR_A_120x22c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A11__DDR_A_110x230 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A10__DDR_A_100x234 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A9__DDR_A_9  0x238 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A8__DDR_A_8  0x23c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A7__DDR_A_7  0x240 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A6__DDR_A_6  0x244 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A5__DDR_A_5  0x248 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A4__DDR_A_4  0x24c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A3__DDR_A_3  0x250 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A2__DDR_A_2  0x254 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A1__DDR_A_1  0x258 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A0__DDR_A_0  0x25c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA2__DDR_BA_20x260 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA1__DDR_BA_10x264 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA0__DDR_BA_00x268 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CAS__DDR_CAS_B   0x26c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CKE__DDR_CKE_0   0x270 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CLK__DDR_CLK_0   0x274 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CS__DDR_CS_B_0   0x278 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D15__DDR_D_150x27c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D14__DDR_D_140x280 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D13__DDR_D_130x284 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D12__DDR_D_120x288 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D11__DDR_D_110x28c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D10__DDR_D_100x290 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D9__DDR_D_9  0x294 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D8__DDR_D_8  0x298 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D7__DDR_D_7  0x29c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D6__DDR_D_6  0x2a0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D5__DDR_D_5  0x2a4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D4__DDR_D_4  0x2a8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D3__DDR_D_3  0x2ac 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D2__DDR_D_2  0x2b0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D1__DDR_D_1  0x2b4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D0__DDR_D_0  0x2b8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM1__DDR_DQM_1  0x2bc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM0__DDR_DQM_0  0x2c0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS1__DDR_DQS_1  0x2c4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS0__DDR_DQS_0  0x2c8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_RAS__DDR_RAS_B   0x2cc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT1__DDR_ODT_0  0x2d4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT0__DDR_ODT_1  0x2d8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1   0x2dc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0   0x2e0 0x000 ALT0 0x0
 #endif
-- 
2.11.0

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