From: Chin Liang See
Add misc support such as EMAC and cpu info printout for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile| 1 +
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
arch/arm/mach-socfpga/misc.c | 76
arch/arm/mach-socfpga/misc_gen5.c | 75 ++-
arch/arm/mach-socfpga/misc_s10.c | 115 ++
5 files changed, 197 insertions(+), 71 deletions(-)
create mode 100644 arch/arm/mach-socfpga/misc_s10.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 910eb6f..b253914 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
+obj-y += misc_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
obj-y += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index 0b65783..8466023 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -8,6 +8,7 @@
#define _MISC_H_
void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+int socfpga_eth_reset(void);
struct bsel {
const char *mode;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 00eff90..cee3296 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -20,11 +20,14 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
struct bsel bsel_str[] = {
{ "rsvd", "Reserved", },
@@ -53,6 +56,7 @@ void enable_caches(void)
#endif
}
+#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void)
{
/* Disable the L2 cache */
@@ -73,6 +77,7 @@ void v7_outer_cache_disable(void)
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
+#endif
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
@@ -136,3 +141,74 @@ int arch_cpu_init(void)
return 0;
}
+
+#if !defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+ if (!phymode)
+ return -EINVAL;
+
+ if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rgmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+#endif
+
+#ifdef CONFIG_ETH_DESIGNWARE
+int socfpga_eth_reset(void)
+{
+ const void *fdt = gd->fdt_blob;
+ struct fdtdec_phandle_args args;
+ const char *phy_mode;
+ u32 phy_modereg;
+ int nodes[3]; /* Max. 3 GMACs */
+ int ret, count;
+ int i, node;
+
+ count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+ COMPAT_ALTERA_SOCFPGA_DWMAC,
+ nodes, ARRAY_SIZE(nodes));
+ for (i = 0; i < count; i++) {
+ node = nodes[i];
+ if (node <= 0)
+ continue;
+
+ ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+"#reset-cells", 1, 0,
+&args);
+ if (ret || (args.args_count != 1)) {
+ debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+ continue;
+ }
+
+ phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+ ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+ if (ret) {
+ debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+ continue;
+ }
+
+ dwmac_deassert_reset(args.args[0], phy_modereg);
+ }
+
+ return 0;
+}
+#else
+int socfpga_eth_reset(void)
+{
+ return 0;
+};
+#endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 91ddb79..6149c8a 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -67,77 +67,6 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
}
-
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymo