Re: [U-Boot] [PATCH v2 06/13] usb: dwc3: add UniPhier specific glue layer

[Marek Vasut]

On 05/16/2016 02:51 PM, Masahiro Yamada wrote:
> Add UniPhier platform specific glue layer to support USB3 Host mode
> on Synopsys DWC3 IP.
> 
> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Marek Vasut 
> ---
> 
> Changes in v2:
>   - Fix build error
>   - Add missing PHY reset deassert

Applied, thanks!

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH v2 06/13] usb: dwc3: add UniPhier specific glue layer

[Masahiro Yamada]

Add UniPhier platform specific glue layer to support USB3 Host mode
on Synopsys DWC3 IP.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

Changes in v2:
  - Fix build error
  - Add missing PHY reset deassert

 drivers/usb/host/Kconfig |   7 +++
 drivers/usb/host/Makefile|   1 +
 drivers/usb/host/dwc3-uniphier.c | 119 +++
 3 files changed, 127 insertions(+)
 create mode 100644 drivers/usb/host/dwc3-uniphier.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 89580cc..a6645dd 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -24,6 +24,13 @@ config USB_XHCI_DWC3
  Say Y or if your system has a Dual Role SuperSpeed
  USB controller based on the DesignWare USB3 IP Core.
 
+config USB_DWC3_UNIPHIER
+   bool "DesignWare USB3 Host Support on UniPhier Platforms"
+   depends on ARCH_UNIPHIER && USB_XHCI_DWC3
+   help
+ Support of USB2/3 functionality in Socionext UniPhier platforms.
+ Say 'Y' here if you have one such device.
+
 endif
 
 config USB_OHCI_GENERIC
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 620d114..8b54fde 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 # xhci
 obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
 obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
diff --git a/drivers/usb/host/dwc3-uniphier.c b/drivers/usb/host/dwc3-uniphier.c
new file mode 100644
index 000..e0358ac
--- /dev/null
+++ b/drivers/usb/host/dwc3-uniphier.c
@@ -0,0 +1,119 @@
+/*
+ * UniPhier Specific Glue Layer for DWC3
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define UNIPHIER_PRO4_DWC3_RESET   0x40
+#define   UNIPHIER_PRO4_DWC3_RESET_XIOMMU  BIT(5)
+#define   UNIPHIER_PRO4_DWC3_RESET_XLINK   BIT(4)
+#define   UNIPHIER_PRO4_DWC3_RESET_PHY_SS  BIT(2)
+
+#define UNIPHIER_PRO5_DWC3_RESET   0x00
+#define   UNIPHIER_PRO5_DWC3_RESET_PHY_S1  BIT(17)
+#define   UNIPHIER_PRO5_DWC3_RESET_PHY_S0  BIT(16)
+#define   UNIPHIER_PRO5_DWC3_RESET_XLINK   BIT(15)
+#define   UNIPHIER_PRO5_DWC3_RESET_XIOMMU  BIT(14)
+
+#define UNIPHIER_PXS2_DWC3_RESET   0x00
+#define   UNIPHIER_PXS2_DWC3_RESET_XLINK   BIT(15)
+
+static int uniphier_pro4_dwc3_init(void __iomem *regs)
+{
+   u32 tmp;
+
+   tmp = readl(regs + UNIPHIER_PRO4_DWC3_RESET);
+   tmp &= ~UNIPHIER_PRO4_DWC3_RESET_PHY_SS;
+   tmp |= UNIPHIER_PRO4_DWC3_RESET_XIOMMU | UNIPHIER_PRO4_DWC3_RESET_XLINK;
+   writel(tmp, regs + UNIPHIER_PRO4_DWC3_RESET);
+
+   return 0;
+}
+
+static int uniphier_pro5_dwc3_init(void __iomem *regs)
+{
+   u32 tmp;
+
+   tmp = readl(regs + UNIPHIER_PRO5_DWC3_RESET);
+   tmp &= ~(UNIPHIER_PRO5_DWC3_RESET_PHY_S1 |
+UNIPHIER_PRO5_DWC3_RESET_PHY_S0);
+   tmp |= UNIPHIER_PRO5_DWC3_RESET_XLINK | UNIPHIER_PRO5_DWC3_RESET_XIOMMU;
+   writel(tmp, regs + UNIPHIER_PRO5_DWC3_RESET);
+
+   return 0;
+}
+
+static int uniphier_pxs2_dwc3_init(void __iomem *regs)
+{
+   u32 tmp;
+
+   tmp = readl(regs + UNIPHIER_PXS2_DWC3_RESET);
+   tmp |= UNIPHIER_PXS2_DWC3_RESET_XLINK;
+   writel(tmp, regs + UNIPHIER_PXS2_DWC3_RESET);
+
+   return 0;
+}
+
+static int uniphier_dwc3_probe(struct udevice *dev)
+{
+   fdt_addr_t base;
+   void __iomem *regs;
+   int (*init)(void __iomem *regs);
+   int ret;
+
+   base = dev_get_addr(dev);
+   if (base == FDT_ADDR_T_NONE)
+   return -EINVAL;
+
+   regs = map_sysmem(base, SZ_32K);
+   if (!regs)
+   return -ENOMEM;
+
+   init = (int (*)(void __iomem *regs))dev_get_driver_data(dev);
+   ret = init(regs);
+   if (ret) {
+   dev_err(dev, "failed to init glue layer\n");
+   return ret;
+   }
+
+   unmap_sysmem(regs);
+
+   return 0;
+}
+
+static const struct udevice_id uniphier_dwc3_match[] = {
+   {
+   .compatible = "socionext,uniphier-pro4-dwc3",
+   .data = (ulong)uniphier_pro4_dwc3_init,
+   },
+   {
+   .compatible = "socionext,uniphier-pro5-dwc3",
+   .data = (ulong)uniphier_pro5_dwc3_init,
+   },
+   {
+   .compatible = "socionext,uniphier-pxs2-dwc3",
+   .data = (ulong)uniphier_pxs2_dwc3_init,
+   },
+   {
+   .compatible = "socionext,uniphier-ld20-dwc3",
+   .data = (ulong)uniphier_pxs2_dwc3_init,
+   },