Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Make changes to chromebook_link.dts since link.dts is gone
- Use intel,ich-spi as the compatible string
arch/x86/dts/chromebook_link.dts | 15 ++-
arch/x86/dts/link.dts| 229 +++
2 files changed, 243 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/dts/link.dts
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 9490b16..45ada61 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -7,6 +7,10 @@
model = Google Link;
compatible = google,link, intel,celeron-ivybridge;
+ aliases {
+ spi0 = /spi;
+ };
+
config {
silent_console = 0;
};
@@ -150,11 +154,20 @@
spi {
#address-cells = 1;
#size-cells = 0;
- compatible = intel,ich9;
+ compatible = intel,ich-spi;
spi-flash@0 {
+ #size-cells = 1;
+ #address-cells = 1;
reg = 0;
compatible = winbond,w25q64, spi-flash;
memory-map = 0xff80 0x0080;
+ rw-mrc-cache {
+ label = rw-mrc-cache;
+ /* Alignment: 4k (for updating) */
+ reg = 0x003e 0x0001;
+ type = wiped;
+ wipe-value = [ff];
+ };
};
};
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
new file mode 100644
index 000..52d8b60
--- /dev/null
+++ b/arch/x86/dts/link.dts
@@ -0,0 +1,229 @@
+/dts-v1/;
+
+/include/ skeleton.dtsi
+/include/ serial.dtsi
+
+/ {
+ model = Google Link;
+ compatible = google,link, intel,celeron-ivybridge;
+
+ aliases {
+ spi0 = /spi;
+ };
+
+ config {
+ silent_console = 0;
+ };
+
+ gpioa {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0 0x10;
+ bank-name = A;
+ };
+
+ gpiob {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x30 0x10;
+ bank-name = B;
+ };
+
+ gpioc {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x40 0x10;
+ bank-name = C;
+ };
+
+ chosen {
+ stdout-path = /serial;
+ };
+
+ spd {
+ compatible = memory-spd;
+ #address-cells = 1;
+ #size-cells = 0;
+ elpida_4Gb_1600_x16 {
+ reg = 0;
+ data = [92 10 0b 03 04 19 02 02
+ 03 52 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 81
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 42 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 02 fe 00
+ 11 52 00 00 00 07 7f 37
+ 45 42 4a 32 30 55 47 36
+ 45 42 55 30 2d 47 4e 2d
+ 46 20 30 20 02 fe 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ samsung_4Gb_1600_1.35v_x16 {
+ reg = 1;
+ data = [92 11 0b 03 04 19 02 02
+
