This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
Signed-off-by: Marty E. Plummer
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31
arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++
arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
board/google/veyron/Kconfig | 16 ++
configs/chromebook_speedy_defconfig | 98
7 files changed, 302 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
create mode 100644 configs/chromebook_speedy_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 44ebc50bfa..eab90216f0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
+ rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3368-lion.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
new file mode 100644
index 00..22ba3490f2
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2015 Google, Inc
+ */
+
+ {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x1>;
+ rockchip,sdram-params = <0x20D266A4 0x5B6 6 53300 6 13 0>;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts
b/arch/arm/dts/rk3288-veyron-speedy.dts
new file mode 100644
index 00..20100bbdee
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-speedy.dts
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron Speedy Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+#include "cros-ec-sbs.dtsi"
+#include "rk3288-veyron-speedy-u-boot.dtsi"
+
+/ {
+ model = "Google Speedy";
+ compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
+"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
+"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
+"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
+"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+
+ panel_regulator: panel-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PB6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_enable_h>;
+ regulator-name = "panel_regulator";
+ startup-delay-us = <10>;
+ vin-supply = <_sys>;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_1v8_disp_en>;
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_wl>;
+ };
+
+ backlight_regulator: backlight-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PB4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pwr_en>;
+ regulator-name = "backlight_regulator";
+ vin-supply = <_sys>;
+ startup-delay-us = <15000>;
+ };
+};
+
+ {
+ power-supply = <_regulator>;
+};
+
+_alert0 {
+ temperature = <65000>;
+};
+
+_alert1 {
+ temperature = <7>;
+};
+
+ {
+ /delete-property/pinctrl-names;
+ /delete-property/pinctrl-0;
+
+ force-hpd;
+};
+
+ {
+ power-supply= <_regulator>;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_int_l>;
+};
+
+ {
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <_clk _cmd _cd_disabled _cd_gpio
+
