Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
On Sat, May 30, 2009 at 09:54:56AM +0200, Magnus Lilja wrote: 2009/5/29 Scott Wood scottw...@freescale.com: The bad block location is typically different (offset 0 rather than 5) with large page flash. I think that's because of the non-standard imlementation of large page support in the i.MX31 NFC. We should have comments in the code explaining what's going on in such cases. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
Hi 2009/6/1 Scott Wood scottw...@freescale.com: On Sat, May 30, 2009 at 09:54:56AM +0200, Magnus Lilja wrote: 2009/5/29 Scott Wood scottw...@freescale.com: The bad block location is typically different (offset 0 rather than 5) with large page flash. I think that's because of the non-standard imlementation of large page support in the i.MX31 NFC. We should have comments in the code explaining what's going on in such cases. Yes, I'll add that. /Magnus ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
Hi
2009/5/30 Magnus Lilja lilja.mag...@gmail.com:
2009/5/29 Scott Wood scottw...@freescale.com:
On Sun, May 03, 2009 at 09:56:57PM +0200, Magnus Lilja wrote:
+static void mx31_nand_page_address(unsigned int page_address)
+{
+ unsigned int page_count;
+
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+
+ /* code only for 2kb flash */
+ if (CFG_NAND_PAGE_SIZE == 0x800) {
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ }
+
+ page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE;
+
+ if (page_address = page_count) {
+ page_count--; /* transform 0x0100 to 0x00ff */
+ do {
+ writew(page_address 0xff, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ page_address = page_address 8;
+ page_count = page_count 8;
+ } while (page_count);
+ }
Does the number of address bytes really need to depend on the size of the
flash chip, or can you base it on the number of non-zero bytes in
page_address (the chip will know when the address phase is over because
ALE drops)?
Ok, will try to look into it.
I did try to output only the non-zero bytes in the page_address but
that didn't work at all, u-boot didn't boot Don't know why though.
/Magnus
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Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
2009/5/29 Scott Wood scottw...@freescale.com:
On Sun, May 03, 2009 at 09:56:57PM +0200, Magnus Lilja wrote:
This patch adds the NAND SPL framework needed to boot i.MX31 boards
from NAND.
Sorry for the delay...
Well, better now than the next time I post these patches.
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h
b/include/asm-arm/arch-mx31/mx31-regs.h
index a8a05c8..3d811d7 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -194,4 +194,94 @@
#define CS5_BASE 0xB600
#define PCMCIA_MEM_BASE 0xC000
+/*
+ * NAND controller
+ */
+#define NFC_BASE_ADDR 0xB800
+
+/*
+ * Addresses for NFC registers
+ */
+#define NFC_BUF_SIZE (NFC_BASE_ADDR + 0xE00)
+#define NFC_BUF_ADDR (NFC_BASE_ADDR + 0xE04)
+#define NFC_FLASH_ADDR (NFC_BASE_ADDR + 0xE06)
+#define NFC_FLASH_CMD (NFC_BASE_ADDR + 0xE08)
The NFC register info should go in its own header, as it exists on more
than just MX31 (e.g. mpc5xxx). Should probably use register structs
rather than #defines.
Yes, will do that. I'm converting the #define's to struct {} and all
accesses will be in the readl/writel(nfc-flash_cmd) format.
diff --git a/nand_spl/nand_boot_mx31.c b/nand_spl/nand_boot_mx31.c
new file mode 100644
index 000..d698d2a
--- /dev/null
+++ b/nand_spl/nand_boot_mx31.c
What in this file is MX31-specific? Even if you don't have other chips
to test on, please try to provide a framework for generic NFC support so
the next chip only needs to tweak the details. That may be as simple as
s/mx31/nfc/.
I'll look into that.
+static void mx31_wait_ready(void)
+{
+ while (1) {
+ if (readw(NFC_CONFIG2) NFC_INT) {
+ uint32_t tmp;
+ /* Reset interrupt flag */
+ tmp = readw(NFC_CONFIG2);
+ tmp = ~NFC_INT;
+ writew(tmp, NFC_CONFIG2);
+ break;
+ }
+ }
+}
while (!(readw(NFC_CONFIG2) NFC_INT))
;
tmp = readw(NFC_CONFIG2);
...
Ok.
+static void mx31_nand_page_address(unsigned int page_address)
+{
+ unsigned int page_count;
+
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+
+ /* code only for 2kb flash */
+ if (CFG_NAND_PAGE_SIZE == 0x800) {
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ }
+
+ page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE;
+
+ if (page_address = page_count) {
+ page_count--; /* transform 0x0100 to 0x00ff */
+ do {
+ writew(page_address 0xff, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ page_address = page_address 8;
+ page_count = page_count 8;
+ } while (page_count);
+ }
Does the number of address bytes really need to depend on the size of the
flash chip, or can you base it on the number of non-zero bytes in
page_address (the chip will know when the address phase is over because
ALE drops)?
Ok, will try to look into it.
+static int mx31_nand_check_ecc(void)
+{
+ unsigned short ecc_status_register;
+
+ ecc_status_register = readw(NFC_ECC_STATUS_RESULT);
+
+ if (ecc_status_register != 0)
+ return 1; /* error */
+ return 0;
+}
How about just return readw(NFC_ECC_STATUS_RESULT);?
ok
+static int mx31_read_page(unsigned int page_address, unsigned char *buf)
+{
+ int i;
+ volatile u32 *p1;
+ volatile u32 *p2;
+ u32 a;
s/p1/src/
s/p2/dest/
s/a/something (just a little) more descriptive/ -- my first guess was
address, but that doesn't seem right...
Ok
No volatile; use I/O accessors.
Yes, already on todo-list.
+ writew(0, NFC_BUF_ADDR); /* read in first 0 buffer */
+ mx31_nand_command(NAND_CMD_READ0);
+ mx31_nand_page_address(page_address);
+
+ if (CFG_NAND_CHIP_SIZE = 0x0800)
+ mx31_nand_command(NAND_CMD_READSTART);
Is it guaranteed that all NAND chips above that size will be large page
and all chips below that size will be small page?
No, I'll change to use the CONFIG_SYS_NAND_PAGE_SIZE to do different
stuff depending on the page size.
+ /* it is hardware specific code for 8-bit 512B NAND-flash spare area */
+ p1++;
+ a = *p1;
+ a = (a 0xff00) 8;
+
+ if (a != 0xff) /* bad block marker verify */
+ return 1; /* potential bad block */
+
+ return 0;
The bad block location is typically different (offset 0 rather than 5)
with large page flash.
I think that's because of the non-standard imlementation of large page
support in the i.MX31 NFC.
+ /* checking first page of each
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
On Sun, May 03, 2009 at 09:56:57PM +0200, Magnus Lilja wrote:
This patch adds the NAND SPL framework needed to boot i.MX31 boards
from NAND.
Sorry for the delay...
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h
b/include/asm-arm/arch-mx31/mx31-regs.h
index a8a05c8..3d811d7 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -194,4 +194,94 @@
#define CS5_BASE 0xB600
#define PCMCIA_MEM_BASE 0xC000
+/*
+ * NAND controller
+ */
+#define NFC_BASE_ADDR0xB800
+
+/*
+ * Addresses for NFC registers
+ */
+#define NFC_BUF_SIZE (NFC_BASE_ADDR + 0xE00)
+#define NFC_BUF_ADDR (NFC_BASE_ADDR + 0xE04)
+#define NFC_FLASH_ADDR (NFC_BASE_ADDR + 0xE06)
+#define NFC_FLASH_CMD(NFC_BASE_ADDR + 0xE08)
The NFC register info should go in its own header, as it exists on more
than just MX31 (e.g. mpc5xxx). Should probably use register structs
rather than #defines.
+/*
+ * Addresses for NFC RAM BUFFER Main area 0
+ */
+#define MAIN_AREA0 (NFC_BASE_ADDR + 0x000)
+#define MAIN_AREA1 (NFC_BASE_ADDR + 0x200)
+#define MAIN_AREA2 (NFC_BASE_ADDR + 0x400)
+#define MAIN_AREA3 (NFC_BASE_ADDR + 0x600)
+
+/*
+ * Addresses for NFC SPARE BUFFER Spare area 0
+ */
+#define SPARE_AREA0 (NFC_BASE_ADDR + 0x800)
+#define SPARE_AREA1 (NFC_BASE_ADDR + 0x810)
+#define SPARE_AREA2 (NFC_BASE_ADDR + 0x820)
+#define SPARE_AREA3 (NFC_BASE_ADDR + 0x830)
NFC_MAIN_AREA0, etc.
diff --git a/nand_spl/nand_boot_mx31.c b/nand_spl/nand_boot_mx31.c
new file mode 100644
index 000..d698d2a
--- /dev/null
+++ b/nand_spl/nand_boot_mx31.c
What in this file is MX31-specific? Even if you don't have other chips
to test on, please try to provide a framework for generic NFC support so
the next chip only needs to tweak the details. That may be as simple as
s/mx31/nfc/.
+static void mx31_wait_ready(void)
+{
+ while (1) {
+ if (readw(NFC_CONFIG2) NFC_INT) {
+ uint32_t tmp;
+ /* Reset interrupt flag */
+ tmp = readw(NFC_CONFIG2);
+ tmp = ~NFC_INT;
+ writew(tmp, NFC_CONFIG2);
+ break;
+ }
+ }
+}
while (!(readw(NFC_CONFIG2) NFC_INT))
;
tmp = readw(NFC_CONFIG2);
...
+static void mx31_nand_page_address(unsigned int page_address)
+{
+ unsigned int page_count;
+
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+
+ /* code only for 2kb flash */
+ if (CFG_NAND_PAGE_SIZE == 0x800) {
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ }
+
+ page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE;
+
+ if (page_address = page_count) {
+ page_count--; /* transform 0x0100 to 0x00ff */
+ do {
+ writew(page_address 0xff, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ page_address = page_address 8;
+ page_count = page_count 8;
+ } while (page_count);
+ }
Does the number of address bytes really need to depend on the size of the
flash chip, or can you base it on the number of non-zero bytes in
page_address (the chip will know when the address phase is over because
ALE drops)?
+static int mx31_nand_check_ecc(void)
+{
+ unsigned short ecc_status_register;
+
+ ecc_status_register = readw(NFC_ECC_STATUS_RESULT);
+
+ if (ecc_status_register != 0)
+ return 1; /* error */
+ return 0;
+}
How about just return readw(NFC_ECC_STATUS_RESULT);?
+static int mx31_read_page(unsigned int page_address, unsigned char *buf)
+{
+ int i;
+ volatile u32 *p1;
+ volatile u32 *p2;
+ u32 a;
s/p1/src/
s/p2/dest/
s/a/something (just a little) more descriptive/ -- my first guess was
address, but that doesn't seem right...
No volatile; use I/O accessors.
+ writew(0, NFC_BUF_ADDR); /* read in first 0 buffer */
+ mx31_nand_command(NAND_CMD_READ0);
+ mx31_nand_page_address(page_address);
+
+ if (CFG_NAND_CHIP_SIZE = 0x0800)
+ mx31_nand_command(NAND_CMD_READSTART);
Is it guaranteed that all NAND chips above that size will be large page
and all chips below that size will be small page?
+ /* it is hardware specific code for 8-bit 512B NAND-flash spare area */
+ p1++;
+ a = *p1;
+ a = (a 0xff00) 8;
+
+ if (a != 0xff) /* bad block marker verify */
+ return 1; /* potential bad block */
+
+ return 0;
The bad block location is typically different (offset 0 rather than 5)
with large page flash.
+ /* checking first page of each block */
I believe some NAND chips may
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
On Tue, May 12, 2009 at 06:03:29AM +0200, Magnus Lilja wrote: As I said in another email: The main purpose of CONFIG_ONENAND_IPL and NAND_SPL in start.S is to change the behaviour a bit, not so much to save some space. Given that those CONFIG_s are used in other places as well to indicate the type of boot I don't think it's good to create a new CONFIG_ that one has to specify in addition to one of the above. Better to define one more in order to test only one... and use the new one for things that are generally applicable to pre-loaders regardless of type. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
2009/5/10 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com: On 21:31 Sun 10 May , Magnus Lilja wrote: 2009/5/9 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com: On 21:56 Sun 03 May , Magnus Lilja wrote: @@ -32,7 +35,7 @@ #include version.h .globl _start _start: b reset -#ifdef CONFIG_ONENAND_IPL +#if defined(CONFIG_ONENAND_IPL) || defined(CONFIG_NAND_SPL) create a better CONFIG_ because we could need for other boot mode A better CONFIG_ than what? CONFIG_NAND_SPL is already used elsewhere in U-boot when booting from NAND. IIRC in this case the purpose is to reduce the size of the start.S to allow more code in the ipl spl The main purpose of CONFIG_ONENAND_IPL and NAND_SPL in start.S is to change the behaviour a bit, not so much to save some space. Regards, Magnus ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
2009/5/10 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com: + + } + + page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE; please use CONFIG_SYS_ or CONFIG_ Will do. and why not detect it? Might be possible, I'll look into it to see if it's doable. tks It's not really doable. In order for this to be worthwhile the nand_flash_ids array from drivers/mtd/nand/nand_ids.c would have to fit into the available space (2048 byte in total) and it didn't even though I removed the text-strings. So it's going to be controlled from the board config file.with CONFIG_something. Regards, Magnus ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
On 21:03 Mon 11 May , Magnus Lilja wrote: 2009/5/10 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com: + + } + + page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE; please use CONFIG_SYS_ or CONFIG_ Will do. and why not detect it? Might be possible, I'll look into it to see if it's doable. tks It's not really doable. In order for this to be worthwhile the nand_flash_ids array from drivers/mtd/nand/nand_ids.c would have to fit into the available space (2048 byte in total) and it didn't even though I removed the text-strings. as you mention here there is only 2K so the start.S was reduced to allow more code so CONFIG_xxx_IPL/SPL do not describe this so please chance it to a better one Best Regards, J. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
2009/5/12 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com: On 21:03 Mon 11 May , Magnus Lilja wrote: 2009/5/10 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com: + + } + + page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE; please use CONFIG_SYS_ or CONFIG_ Will do. and why not detect it? Might be possible, I'll look into it to see if it's doable. tks It's not really doable. In order for this to be worthwhile the nand_flash_ids array from drivers/mtd/nand/nand_ids.c would have to fit into the available space (2048 byte in total) and it didn't even though I removed the text-strings. as you mention here there is only 2K so the start.S was reduced to allow more code so CONFIG_xxx_IPL/SPL do not describe this so please chance it to a better one As I said in another email: The main purpose of CONFIG_ONENAND_IPL and NAND_SPL in start.S is to change the behaviour a bit, not so much to save some space. Given that those CONFIG_s are used in other places as well to indicate the type of boot I don't think it's good to create a new CONFIG_ that one has to specify in addition to one of the above. Regards, Magnus Best Regards, J. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
2009/5/9 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com:
On 21:56 Sun 03 May , Magnus Lilja wrote:
@@ -32,7 +35,7 @@
#include version.h
.globl _start
_start: b reset
-#ifdef CONFIG_ONENAND_IPL
+#if defined(CONFIG_ONENAND_IPL) || defined(CONFIG_NAND_SPL)
create a better CONFIG_
because we could need for other boot mode
A better CONFIG_ than what? CONFIG_NAND_SPL is already used elsewhere
in U-boot when booting from NAND.
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
@@ -156,9 +159,9 @@ relocate: /* relocate U-Boot to
RAM */
adr r0, _start /* r0 - current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
-#ifndef CONFIG_ONENAND_IPL
+#if !defined(CONFIG_ONENAND_IPL) !defined(CONFIG_NAND_SPL)
beq stack_setup
-#endif /* CONFIG_ONENAND_IPL */
+#endif /* !CONFIG_ONENAND_IPL !CONFIG_NAND_SPL*/
#endif /* CONFIG_ONENAND_IPL */
+
snip
diff --git a/nand_spl/nand_boot_mx31.c b/nand_spl/nand_boot_mx31.c
new file mode 100644
index 000..d698d2a
--- /dev/null
+++ b/nand_spl/nand_boot_mx31.c
@@ -0,0 +1,223 @@
snip
+static void mx31_nand_page_address(unsigned int page_address)
+{
+ unsigned int page_count;
+
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+
+ /* code only for 2kb flash */
+ if (CFG_NAND_PAGE_SIZE == 0x800) {
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ }
+
+ page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE;
please use CONFIG_SYS_ or CONFIG_
Will do.
and why not detect it?
Might be possible, I'll look into it to see if it's doable.
Thanks; Magnus
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Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
On 21:31 Sun 10 May , Magnus Lilja wrote: 2009/5/9 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com: On 21:56 Sun 03 May , Magnus Lilja wrote: @@ -32,7 +35,7 @@ #include version.h .globl _start _start: b reset -#ifdef CONFIG_ONENAND_IPL +#if defined(CONFIG_ONENAND_IPL) || defined(CONFIG_NAND_SPL) create a better CONFIG_ because we could need for other boot mode A better CONFIG_ than what? CONFIG_NAND_SPL is already used elsewhere in U-boot when booting from NAND. IIRC in this case the purpose is to reduce the size of the start.S to allow more code in the ipl spl ldr pc, _hang ldr pc, _hang ldr pc, _hang @@ -156,9 +159,9 @@ relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 - current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) !defined(CONFIG_NAND_SPL) beq stack_setup -#endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_ONENAND_IPL !CONFIG_NAND_SPL*/ #endif /* CONFIG_ONENAND_IPL */ + + } + + page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE; please use CONFIG_SYS_ or CONFIG_ Will do. and why not detect it? Might be possible, I'll look into it to see if it's doable. tks Best Regards, J. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
On 21:56 Sun 03 May , Magnus Lilja wrote:
This patch adds the NAND SPL framework needed to boot i.MX31 boards
from NAND.
The patch is based on the work by Maxim Artamonov
scn1874 at yandex.ru (which was signed-off-by him).
so please add it too
and please fix the @
Signed-off-by: Magnus Lilja lilja.mag...@gmail.com
---
cpu/arm1136/start.S | 29 +++--
include/asm-arm/arch-mx31/mx31-regs.h | 90 +
nand_spl/nand_boot_mx31.c | 223
+
3 files changed, 331 insertions(+), 11 deletions(-)
create mode 100644 nand_spl/nand_boot_mx31.c
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
index e622338..9bbbaf1 100644
--- a/cpu/arm1136/start.S
+++ b/cpu/arm1136/start.S
@@ -1,6 +1,9 @@
/*
* armboot - Startup Code for OMP2420/ARM1136 CPU-core
*
+ *
+ * Copyright (c) 2008 Maxim Artamonov, scn1874 at yandex.ru
+ *
please remove
* Copyright (c) 2004 Texas Instruments r-woodru...@ti.com
*
* Copyright (c) 2001 Marius Gr�ger m...@sysgo.de
@@ -32,7 +35,7 @@
#include version.h
.globl _start
_start: breset
-#ifdef CONFIG_ONENAND_IPL
+#if defined(CONFIG_ONENAND_IPL) || defined(CONFIG_NAND_SPL)
create a better CONFIG_
because we could need for other boot mode
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
@@ -156,9 +159,9 @@ relocate: /* relocate U-Boot to
RAM */
adr r0, _start /* r0 - current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
-#ifndef CONFIG_ONENAND_IPL
+#if !defined(CONFIG_ONENAND_IPL) !defined(CONFIG_NAND_SPL)
beq stack_setup
-#endif /* CONFIG_ONENAND_IPL */
+#endif /* !CONFIG_ONENAND_IPL !CONFIG_NAND_SPL*/
#endif /* CONFIG_ONENAND_IPL */
+
snip
diff --git a/nand_spl/nand_boot_mx31.c b/nand_spl/nand_boot_mx31.c
new file mode 100644
index 000..d698d2a
--- /dev/null
+++ b/nand_spl/nand_boot_mx31.c
@@ -0,0 +1,223 @@
snip
+static void mx31_nand_page_address(unsigned int page_address)
+{
+ unsigned int page_count;
+
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+
+ /* code only for 2kb flash */
+ if (CFG_NAND_PAGE_SIZE == 0x800) {
+ writew(0x00, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ }
+
+ page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE;
please use CONFIG_SYS_ or CONFIG_
and why not detect it?
+
+ if (page_address = page_count) {
+ page_count--; /* transform 0x0100 to 0x00ff */
+ do {
+ writew(page_address 0xff, NFC_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_CONFIG2);
+ mx31_wait_ready();
+ page_address = page_address 8;
+ page_count = page_count 8;
+ } while (page_count);
+ }
+}
+
snip
+
+static int nand_load(unsigned int from, unsigned int size, unsigned char
*buf)
+{
+ int i, bb;
+
+ mx31_nand_init();
+
+ /* convert from to page number */
+ from = from / CFG_NAND_PAGE_SIZE;
+
+ i = 0;
+
+ while (i (size/CFG_NAND_PAGE_SIZE)) {
+ if ((from * CFG_NAND_PAGE_SIZE) = CFG_NAND_CHIP_SIZE)
+ return 2; /* memory segment violation */
+
+ bb = mx31_read_page(from, buf);
+
+ if (bb 0)
+ return -1;
+
+ /* checking first page of each block */
+ /* if this page has bb marker, then skip whole block */
+ if ((!(from % CFG_NAND_PAGES_PER_BLOCK)) bb) {
please use CONFIG_SYS_ or CONFIG_
and why not detect it?
+ from = from + CFG_NAND_PAGES_PER_BLOCK;
+ } else {
+ i++;
+ from++;
+ buf = buf + CFG_NAND_PAGE_SIZE;
please use CONFIG_SYS_ or CONFIG_
and why not detect it?
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
+void nand_boot(void)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ /* CFG_NAND_U_BOOT_OFFS and CFG_NAND_U_BOOT_SIZE must */
please use CONFIG_SYS_ or CONFIG_
and so on
+ /* be aligned to full pages */
please use this style of multiple ligne comment
/*
*
*/
Best Regards,
J.
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[U-Boot] [PATCH v2 1/3] MX31: Add NAND SPL for i.MX31.
This patch adds the NAND SPL framework needed to boot i.MX31 boards from NAND. The patch is based on the work by Maxim Artamonov scn1874 at yandex.ru (which was signed-off-by him). Signed-off-by: Magnus Lilja lilja.mag...@gmail.com --- cpu/arm1136/start.S | 29 +++-- include/asm-arm/arch-mx31/mx31-regs.h | 90 + nand_spl/nand_boot_mx31.c | 223 + 3 files changed, 331 insertions(+), 11 deletions(-) create mode 100644 nand_spl/nand_boot_mx31.c diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index e622338..9bbbaf1 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -1,6 +1,9 @@ /* * armboot - Startup Code for OMP2420/ARM1136 CPU-core * + * + * Copyright (c) 2008 Maxim Artamonov, scn1874 at yandex.ru + * * Copyright (c) 2004 Texas Instruments r-woodru...@ti.com * * Copyright (c) 2001 Marius Gröger m...@sysgo.de @@ -32,7 +35,7 @@ #include version.h .globl _start _start: b reset -#ifdef CONFIG_ONENAND_IPL +#if defined(CONFIG_ONENAND_IPL) || defined(CONFIG_NAND_SPL) ldr pc, _hang ldr pc, _hang ldr pc, _hang @@ -156,9 +159,9 @@ relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 - current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) !defined(CONFIG_NAND_SPL) beq stack_setup -#endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_ONENAND_IPL !CONFIG_NAND_SPL*/ ldr r2, _armboot_start ldr r3, _bss_start @@ -175,7 +178,7 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ -#ifdef CONFIG_ONENAND_IPL +#if defined(CONFIG_ONENAND_IPL) || defined (CONFIG_NAND_SPL) sub sp, r0, #128/* leave 32 words for abort-stack */ #else sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ @@ -184,14 +187,14 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack*/ -#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_ONENAND_IPL || CONFIG_NAND_SPL*/ clear_bss: ldr r0, _bss_start /* find start of bss segment*/ ldr r1, _bss_end/* stop here*/ mov r2, #0x /* clear*/ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) !defined(CONFIG_NAND_SPL) clbss_l:strr2, [r0]/* clear loop...*/ add r0, r0, #4 cmp r0, r1 @@ -200,12 +203,15 @@ clbss_l:str r2, [r0]/* clear loop...*/ ldr pc, _start_armboot +#ifdef CONFIG_NAND_SPL +_start_armboot: .word nand_boot +#else #ifdef CONFIG_ONENAND_IPL _start_armboot: .word start_oneboot #else _start_armboot: .word start_armboot -#endif - +#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_NAND_SPL */ /* * @@ -244,7 +250,7 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) !defined(CONFIG_NAND_SPL) /* * * @@ -357,12 +363,12 @@ cpu_init_crit: .macro get_fiq_stack@ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_ONENAND_IPL !CONFIG_NAND_SPL*/ /* * exception handlers */ -#ifdef CONFIG_ONENAND_IPL +#if defined(CONFIG_ONENAND_IPL) || defined(CONFIG_NAND_SPL) .align 5 do_hang: ldr sp, _TEXT_BASE /* use 32 words about stack */ @@ -436,3 +442,4 @@ arm1136_cache_flush: mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache mov pc, lr @ back to caller #endif /* CONFIG_ONENAND_IPL */ + diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index a8a05c8..3d811d7 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -194,4 +194,94 @@ #define CS5_BASE 0xB600 #define PCMCIA_MEM_BASE0xC000 +/* + * NAND controller + */ +#define NFC_BASE_ADDR 0xB800 + +/* + * Addresses for NFC registers + */ +#define NFC_BUF_SIZE (NFC_BASE_ADDR + 0xE00) +#define NFC_BUF_ADDR (NFC_BASE_ADDR + 0xE04) +#define
