Re: [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver
On Fri, Jul 5, 2019 at 11:58 AM Bin Meng wrote: > > On Sat, Jun 29, 2019 at 2:56 PM Anup Patel wrote: > > > > From: Bhargav Shah > > > > This patch adds SiFive SPI driver. The driver is 100% DM driver > > and it determines input clock using clk framework. > > > > The SiFive SPI block is found on SiFive FU540 SOC and is used to > > access flash and MMC devices on SiFive Unleashed board. > > > > This driver implementation is inspired from the Linux SiFive SPI > > driver available in Linux-5.2 or higher and SiFive FSBL sources. > > > > Signed-off-by: Bhargav Shah > > Signed-off-by: Anup Patel > > --- > > drivers/spi/Kconfig | 8 + > > drivers/spi/Makefile | 1 + > > drivers/spi/spi-sifive.c | 405 +++ > > 3 files changed, 414 insertions(+) > > create mode 100644 drivers/spi/spi-sifive.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > > index eb32f082fe..2712bad310 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -224,6 +224,14 @@ config SANDBOX_SPI > > }; > > }; > > > > +config SIFIVE_SPI > > + bool "SiFive SPI driver" > > + help > > + This driver supports the SiFive SPI IP. If unsure say N. > > + Enable the SiFive SPI controller driver. > > + > > + The SiFive SPI controller driver is found on various SiFive SoCs. > > + > > config SPI_SUNXI > > bool "Allwinner SoC SPI controllers" > > help > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > > index 8be9a4baa2..09a9d3697e 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o > > obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o > > obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o > > obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o > > +obj-$(CONFIG_SIFIVE_SPI) += spi-sifive.o > > obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o > > obj-$(CONFIG_SH_SPI) += sh_spi.o > > obj-$(CONFIG_SH_QSPI) += sh_qspi.o > > diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c > > new file mode 100644 > > index 00..70eebc0463 > > --- /dev/null > > +++ b/drivers/spi/spi-sifive.c > > @@ -0,0 +1,405 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2018 SiFive, Inc. > > + * Copyright 2019 Bhargav Shah > > + * > > + * SiFive SPI controller driver (master mode only) > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +DECLARE_GLOBAL_DATA_PTR; > > This is not needed. Okay, I will drop it. > > > + > > +#define SIFIVE_SPI_MAX_CS 32 > > + > > +#define SIFIVE_SPI_DEFAULT_DEPTH 8 > > +#define SIFIVE_SPI_DEFAULT_BITS8 > > + > > +/* register offsets */ > > +#define SIFIVE_SPI_REG_SCKDIV0x00 /* Serial clock divisor */ > > +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ > > +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ > > +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ > > +#define SIFIVE_SPI_REG_CSMODE0x18 /* Chip select mode */ > > +#define SIFIVE_SPI_REG_DELAY00x28 /* Delay control 0 */ > > +#define SIFIVE_SPI_REG_DELAY10x2c /* Delay control 1 */ > > +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ > > +#define SIFIVE_SPI_REG_TXDATA0x48 /* Tx FIFO data */ > > +#define SIFIVE_SPI_REG_RXDATA0x4c /* Rx FIFO data */ > > +#define SIFIVE_SPI_REG_TXMARK0x50 /* Tx FIFO watermark */ > > +#define SIFIVE_SPI_REG_RXMARK0x54 /* Rx FIFO watermark */ > > +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface > > control */ > > +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction > > format */ > > +#define SIFIVE_SPI_REG_IE0x70 /* Interrupt Enable Register > > */ > > +#define SIFIVE_SPI_REG_IP0x74 /* Interrupt Pendings > > Register */ > > + > > +/* sckdiv bits */ > > +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU > > + > > +/* sckmode bits */ > > +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) > > +#define SIFIVE_SPI_SCKMODE_POL BIT(1) > > +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ > > + SIFIVE_SPI_SCKMODE_POL) > > + > > +/* csmode bits */ > > +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U > > +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U > > +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U > > + > > +/* delay0 bits */ > > +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) > > +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU > > +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) > > +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) > > + > > +/* delay1 bits */ > > +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) > > +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU > > +#de
Re: [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver
On Sat, Jun 29, 2019 at 2:56 PM Anup Patel wrote: > > From: Bhargav Shah > > This patch adds SiFive SPI driver. The driver is 100% DM driver > and it determines input clock using clk framework. > > The SiFive SPI block is found on SiFive FU540 SOC and is used to > access flash and MMC devices on SiFive Unleashed board. > > This driver implementation is inspired from the Linux SiFive SPI > driver available in Linux-5.2 or higher and SiFive FSBL sources. > > Signed-off-by: Bhargav Shah > Signed-off-by: Anup Patel > --- > drivers/spi/Kconfig | 8 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-sifive.c | 405 +++ > 3 files changed, 414 insertions(+) > create mode 100644 drivers/spi/spi-sifive.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index eb32f082fe..2712bad310 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -224,6 +224,14 @@ config SANDBOX_SPI > }; > }; > > +config SIFIVE_SPI > + bool "SiFive SPI driver" > + help > + This driver supports the SiFive SPI IP. If unsure say N. > + Enable the SiFive SPI controller driver. > + > + The SiFive SPI controller driver is found on various SiFive SoCs. > + > config SPI_SUNXI > bool "Allwinner SoC SPI controllers" > help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 8be9a4baa2..09a9d3697e 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o > obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o > obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o > obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o > +obj-$(CONFIG_SIFIVE_SPI) += spi-sifive.o > obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o > obj-$(CONFIG_SH_SPI) += sh_spi.o > obj-$(CONFIG_SH_QSPI) += sh_qspi.o > diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c > new file mode 100644 > index 00..70eebc0463 > --- /dev/null > +++ b/drivers/spi/spi-sifive.c > @@ -0,0 +1,405 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 SiFive, Inc. > + * Copyright 2019 Bhargav Shah > + * > + * SiFive SPI controller driver (master mode only) > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +DECLARE_GLOBAL_DATA_PTR; This is not needed. > + > +#define SIFIVE_SPI_MAX_CS 32 > + > +#define SIFIVE_SPI_DEFAULT_DEPTH 8 > +#define SIFIVE_SPI_DEFAULT_BITS8 > + > +/* register offsets */ > +#define SIFIVE_SPI_REG_SCKDIV0x00 /* Serial clock divisor */ > +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ > +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ > +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ > +#define SIFIVE_SPI_REG_CSMODE0x18 /* Chip select mode */ > +#define SIFIVE_SPI_REG_DELAY00x28 /* Delay control 0 */ > +#define SIFIVE_SPI_REG_DELAY10x2c /* Delay control 1 */ > +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ > +#define SIFIVE_SPI_REG_TXDATA0x48 /* Tx FIFO data */ > +#define SIFIVE_SPI_REG_RXDATA0x4c /* Rx FIFO data */ > +#define SIFIVE_SPI_REG_TXMARK0x50 /* Tx FIFO watermark */ > +#define SIFIVE_SPI_REG_RXMARK0x54 /* Rx FIFO watermark */ > +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control > */ > +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction > format */ > +#define SIFIVE_SPI_REG_IE0x70 /* Interrupt Enable Register */ > +#define SIFIVE_SPI_REG_IP0x74 /* Interrupt Pendings Register > */ > + > +/* sckdiv bits */ > +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU > + > +/* sckmode bits */ > +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) > +#define SIFIVE_SPI_SCKMODE_POL BIT(1) > +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ > + SIFIVE_SPI_SCKMODE_POL) > + > +/* csmode bits */ > +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U > +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U > +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U > + > +/* delay0 bits */ > +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) > +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU > +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) > +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) > + > +/* delay1 bits */ > +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) > +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU > +#define SIFIVE_SPI_DELAY1_INTERXFR(x)((u32)(x) << 16) > +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) > + > +/* fmt bits */ > +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U > +#define SIFIVE_SPI_FMT_PROTO_DUAL1U > +#define SIFIVE_SPI_FMT_PROTO_QUAD2U > +#define SIFIVE_SPI_FMT_PROTO_MASK3U > +#define SIFI
[U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver
From: Bhargav Shah This patch adds SiFive SPI driver. The driver is 100% DM driver and it determines input clock using clk framework. The SiFive SPI block is found on SiFive FU540 SOC and is used to access flash and MMC devices on SiFive Unleashed board. This driver implementation is inspired from the Linux SiFive SPI driver available in Linux-5.2 or higher and SiFive FSBL sources. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 405 +++ 3 files changed, 414 insertions(+) create mode 100644 drivers/spi/spi-sifive.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index eb32f082fe..2712bad310 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -224,6 +224,14 @@ config SANDBOX_SPI }; }; +config SIFIVE_SPI + bool "SiFive SPI driver" + help + This driver supports the SiFive SPI IP. If unsure say N. + Enable the SiFive SPI controller driver. + + The SiFive SPI controller driver is found on various SiFive SoCs. + config SPI_SUNXI bool "Allwinner SoC SPI controllers" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4baa2..09a9d3697e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o +obj-$(CONFIG_SIFIVE_SPI) += spi-sifive.o obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c new file mode 100644 index 00..70eebc0463 --- /dev/null +++ b/drivers/spi/spi-sifive.c @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 SiFive, Inc. + * Copyright 2019 Bhargav Shah + * + * SiFive SPI controller driver (master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SIFIVE_SPI_MAX_CS 32 + +#define SIFIVE_SPI_DEFAULT_DEPTH 8 +#define SIFIVE_SPI_DEFAULT_BITS8 + +/* register offsets */ +#define SIFIVE_SPI_REG_SCKDIV0x00 /* Serial clock divisor */ +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ +#define SIFIVE_SPI_REG_CSMODE0x18 /* Chip select mode */ +#define SIFIVE_SPI_REG_DELAY00x28 /* Delay control 0 */ +#define SIFIVE_SPI_REG_DELAY10x2c /* Delay control 1 */ +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ +#define SIFIVE_SPI_REG_TXDATA0x48 /* Tx FIFO data */ +#define SIFIVE_SPI_REG_RXDATA0x4c /* Rx FIFO data */ +#define SIFIVE_SPI_REG_TXMARK0x50 /* Tx FIFO watermark */ +#define SIFIVE_SPI_REG_RXMARK0x54 /* Rx FIFO watermark */ +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */ +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */ +#define SIFIVE_SPI_REG_IE0x70 /* Interrupt Enable Register */ +#define SIFIVE_SPI_REG_IP0x74 /* Interrupt Pendings Register */ + +/* sckdiv bits */ +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU + +/* sckmode bits */ +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) +#define SIFIVE_SPI_SCKMODE_POL BIT(1) +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ + SIFIVE_SPI_SCKMODE_POL) + +/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U + +/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) + +/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x)((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) + +/* fmt bits */ +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U +#define SIFIVE_SPI_FMT_PROTO_DUAL1U +#define SIFIVE_SPI_FMT_PROTO_QUAD2U +#define SIFIVE_SPI_FMT_PROTO_MASK3U +#define SIFIVE_SPI_FMT_ENDIANBIT(2) +#define SIFIVE_SPI_FMT_DIR BIT(3) +#define SIFIVE_SPI_FMT_LEN(x)((u32)(x) << 16) +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16) + +/* txdata bits */ +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_TXDATA_FULL BIT(31) + +/* rxdata bits
