Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:35 +0200, Marek Vasut wrote:
> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Add DDR driver suppport for Arria 10.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
> > > >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> > > >  drivers/ddr/altera/sdram_arria10.c | 735
> > > > +
> > > >  3 files changed, 839 insertions(+), 1 deletion(-)
> > > >  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index 4a9754e..b833fc2 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -10,6 +10,8 @@
> > > >  
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  #include 
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#include 
> > > >  #endif
> > > >  
> > > >  #endif
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > index 1d7b7c1..7af9431 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > @@ -1,5 +1,5 @@
> > > >  /*
> > > > - * Copyright (C) 2015-2017 Intel Corporation 
> > > > + * Copyright (C) 2017 Intel Corporation 
> > > >   *
> > > >   * SPDX-License-Identifier:GPL-2.0
> > > >   */
> > > > @@ -8,6 +8,7 @@
> > > >  #define _SOCFPGA_SDRAM_ARRIA10_H_
> > > >  
> > > >  #ifndef __ASSEMBLY__
> > > > +int ddr_calibration_sequence(void);
> > > >  
> > > >  struct socfpga_ecc_hmc {
> > > >     u32 ip_rev_id;
> > > > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
> > > >     u32 niosreserve1;
> > > >     u32 niosreserve2;
> > > >  };
> > > > +
> > > > +union dramaddrw_reg {
> > > > +   struct {
> > > > +   u32 cfg_col_addr_width:5;
> > > > +   u32 cfg_row_addr_width:5;
> > > > +   u32 cfg_bank_addr_width:4;
> > > > +   u32 cfg_bank_group_addr_width:2;
> > > > +   u32 cfg_cs_addr_width:3;
> > > > +   u32 reserved:13;
> > > > +   };
> > > Use regular macros for bitfields, not this crap.
> > > 
> > Why regular macros is prefered? Above implementation improve
> > readability, simplify the implementation and saving memory.
> Because that's how U-Boot does it (and the above afair breaks on
> different endianness).
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > +   u32 word;
> > > > +};
> > > > +
> > > > +union ctrlcfg0_reg {
> > > > +   struct {
> > > > +   u32 cfg_mem_type:4;
> > > > +   u32 cfg_dimm_type:3;
> > > > +   u32 cfg_ac_pos:2;
> > > > +   u32 cfg_ctrl_burst_len:5;
> > > > +   u32 reserved:18;  /* Other fields unused */
> > > > +   };
> > > > +   u32 word;
> > > > +};
> > > [...]
> [...]
> 
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Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Marek Vasut]

On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Add DDR driver suppport for Arria 10.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
>>>  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
>>>  drivers/ddr/altera/sdram_arria10.c | 735
>>> +
>>>  3 files changed, 839 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/ddr/altera/sdram_arria10.c
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> index 4a9754e..b833fc2 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> @@ -10,6 +10,8 @@
>>>  
>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  #include 
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#include 
>>>  #endif
>>>  
>>>  #endif
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> index 1d7b7c1..7af9431 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> @@ -1,5 +1,5 @@
>>>  /*
>>> - * Copyright (C) 2015-2017 Intel Corporation 
>>> + * Copyright (C) 2017 Intel Corporation 
>>>   *
>>>   * SPDX-License-Identifier:GPL-2.0
>>>   */
>>> @@ -8,6 +8,7 @@
>>>  #define _SOCFPGA_SDRAM_ARRIA10_H_
>>>  
>>>  #ifndef __ASSEMBLY__
>>> +int ddr_calibration_sequence(void);
>>>  
>>>  struct socfpga_ecc_hmc {
>>>     u32 ip_rev_id;
>>> @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
>>>     u32 niosreserve1;
>>>     u32 niosreserve2;
>>>  };
>>> +
>>> +union dramaddrw_reg {
>>> +   struct {
>>> +   u32 cfg_col_addr_width:5;
>>> +   u32 cfg_row_addr_width:5;
>>> +   u32 cfg_bank_addr_width:4;
>>> +   u32 cfg_bank_group_addr_width:2;
>>> +   u32 cfg_cs_addr_width:3;
>>> +   u32 reserved:13;
>>> +   };
>> Use regular macros for bitfields, not this crap.
>>
> Why regular macros is prefered? Above implementation improve
> readability, simplify the implementation and saving memory.

Because that's how U-Boot does it (and the above afair breaks on
different endianness).

>>>
>>> +   u32 word;
>>> +};
>>> +
>>> +union ctrlcfg0_reg {
>>> +   struct {
>>> +   u32 cfg_mem_type:4;
>>> +   u32 cfg_dimm_type:3;
>>> +   u32 cfg_ac_pos:2;
>>> +   u32 cfg_ctrl_burst_len:5;
>>> +   u32 reserved:18;  /* Other fields unused */
>>> +   };
>>> +   u32 word;
>>> +};
>> [...]

[...]

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Add DDR driver suppport for Arria 10.
> > 
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
> >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> >  drivers/ddr/altera/sdram_arria10.c | 735
> > +
> >  3 files changed, 839 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > index 4a9754e..b833fc2 100644
> > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > @@ -10,6 +10,8 @@
> >  
> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  #include 
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#include 
> >  #endif
> >  
> >  #endif
> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > index 1d7b7c1..7af9431 100644
> > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright (C) 2015-2017 Intel Corporation 
> > + * Copyright (C) 2017 Intel Corporation 
> >   *
> >   * SPDX-License-Identifier:GPL-2.0
> >   */
> > @@ -8,6 +8,7 @@
> >  #define _SOCFPGA_SDRAM_ARRIA10_H_
> >  
> >  #ifndef __ASSEMBLY__
> > +int ddr_calibration_sequence(void);
> >  
> >  struct socfpga_ecc_hmc {
> >     u32 ip_rev_id;
> > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
> >     u32 niosreserve1;
> >     u32 niosreserve2;
> >  };
> > +
> > +union dramaddrw_reg {
> > +   struct {
> > +   u32 cfg_col_addr_width:5;
> > +   u32 cfg_row_addr_width:5;
> > +   u32 cfg_bank_addr_width:4;
> > +   u32 cfg_bank_group_addr_width:2;
> > +   u32 cfg_cs_addr_width:3;
> > +   u32 reserved:13;
> > +   };
> Use regular macros for bitfields, not this crap.
> 
Why regular macros is prefered? Above implementation improve
readability, simplify the implementation and saving memory.
> > 
> > +   u32 word;
> > +};
> > +
> > +union ctrlcfg0_reg {
> > +   struct {
> > +   u32 cfg_mem_type:4;
> > +   u32 cfg_dimm_type:3;
> > +   u32 cfg_ac_pos:2;
> > +   u32 cfg_ctrl_burst_len:5;
> > +   u32 reserved:18;  /* Other fields unused */
> > +   };
> > +   u32 word;
> > +};
> [...]
> 
> > 
> > diff --git a/drivers/ddr/altera/sdram_arria10.c
> > b/drivers/ddr/altera/sdram_arria10.c
> > new file mode 100644
> > index 000..f22a726
> > --- /dev/null
> > +++ b/drivers/ddr/altera/sdram_arria10.c
> > @@ -0,0 +1,735 @@
> > +/*
> > + * Copyright (C) 2017 Intel Corporation 
> > + *
> > + * SPDX-License-Identifier:GPL-2.0
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> Why does an SDRAM init driver need access to ns16550 UART , MMC and
> NAND ?
> 
I will remove them.
> > 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static void sdram_mmr_init(void);
> > +static unsigned long long sdram_size_calc(void);
> > +
> > +/* FAWBANK - Number of Bank of a given device involved in the FAW
> > period. */
> > +#define ARRIA10_SDR_ACTIVATE_FAWBANK   (0x1)
> > +
> > +#define ARRIA_DDR_CONFIG(A, B, C, R)   ((A<<24)|(B<<16)|(C<<8
> > )|R)
> Missing parenthesis around (A), (B) etc. ...
> 
Okay.
> > 
> > +#define DDR_CONFIG_ELEMENTS(sizeof(ddr_config)/sizeof(u32)
> > )
> So this is ARRAY_SIZE() ?
> 
Yes. i will use ARRAY_SIZE().
> > 
> > +#define DDR_REG_SEQ2CORE0xFFD0507C
> > +#define DDR_REG_CORE2SEQ0xFFD05078
> > +#define DDR_READ_LATENCY_DELAY 40
> > +#define DDR_SIZE_2GB_HEX   0x8000
> > +#define DDR_MAX_TRIES  0x0010
> > +
> > +#define IO48_MMR_DRAMSTS   0xFFCFA0EC
> > +#define IO48_MMR_NIOS2_RESERVE00xFFCFA110
> > +#define IO48_MMR_NIOS2_RESERVE10xFFCFA114
> > +#define IO48_MMR_NIOS2_RESERVE20xFFCFA118
> > +
> > +#define SEQ2CORE_MASK  0xF
> > +#define CORE2SEQ_INT_REQ   0xF
> > +#define SEQ2CORE_INT_RESP_BIT  3
> > +
> > +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
> > +   (void *)SOCFPGA_SDR_ADDRESS;
> > +static const struct socfpga_noc_ddr_scheduler
> > *socfpga_noc_ddr_scheduler_base =
> > +   (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
> > +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
> > +   *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
> > +   (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
> > +static const struct socfpga_noc_fw_ddr_l3
> > *socfpga_noc_fw_ddr_l3_base =
> > +   (void 

Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> Add DDR driver suppport for Arria 10.
> 
> Signed-off-by: Tien Fong Chee 
> ---
>  arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
>  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
>  drivers/ddr/altera/sdram_arria10.c | 735 
> +
>  3 files changed, 839 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
> b/arch/arm/mach-socfpga/include/mach/sdram.h
> index 4a9754e..b833fc2 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> @@ -10,6 +10,8 @@
>  
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #include 
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include 
>  #endif
>  
>  #endif
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h 
> b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> index 1d7b7c1..7af9431 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (C) 2015-2017 Intel Corporation 
> + * Copyright (C) 2017 Intel Corporation 
>   *
>   * SPDX-License-Identifier:  GPL-2.0
>   */
> @@ -8,6 +8,7 @@
>  #define _SOCFPGA_SDRAM_ARRIA10_H_
>  
>  #ifndef __ASSEMBLY__
> +int ddr_calibration_sequence(void);
>  
>  struct socfpga_ecc_hmc {
>   u32 ip_rev_id;
> @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
>   u32 niosreserve1;
>   u32 niosreserve2;
>  };
> +
> +union dramaddrw_reg {
> + struct {
> + u32 cfg_col_addr_width:5;
> + u32 cfg_row_addr_width:5;
> + u32 cfg_bank_addr_width:4;
> + u32 cfg_bank_group_addr_width:2;
> + u32 cfg_cs_addr_width:3;
> + u32 reserved:13;
> + };

Use regular macros for bitfields, not this crap.

> + u32 word;
> +};
> +
> +union ctrlcfg0_reg {
> + struct {
> + u32 cfg_mem_type:4;
> + u32 cfg_dimm_type:3;
> + u32 cfg_ac_pos:2;
> + u32 cfg_ctrl_burst_len:5;
> + u32 reserved:18;  /* Other fields unused */
> + };
> + u32 word;
> +};

[...]

> diff --git a/drivers/ddr/altera/sdram_arria10.c 
> b/drivers/ddr/altera/sdram_arria10.c
> new file mode 100644
> index 000..f22a726
> --- /dev/null
> +++ b/drivers/ddr/altera/sdram_arria10.c
> @@ -0,0 +1,735 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 

Why does an SDRAM init driver need access to ns16550 UART , MMC and NAND ?

> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static void sdram_mmr_init(void);
> +static unsigned long long sdram_size_calc(void);
> +
> +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
> +#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
> +
> +#define ARRIA_DDR_CONFIG(A, B, C, R) ((A<<24)|(B<<16)|(C<<8)|R)

Missing parenthesis around (A), (B) etc. ...

> +#define DDR_CONFIG_ELEMENTS  (sizeof(ddr_config)/sizeof(u32))

So this is ARRAY_SIZE() ?

> +#define DDR_REG_SEQ2CORE0xFFD0507C
> +#define DDR_REG_CORE2SEQ0xFFD05078
> +#define DDR_READ_LATENCY_DELAY   40
> +#define DDR_SIZE_2GB_HEX 0x8000
> +#define DDR_MAX_TRIES0x0010
> +
> +#define IO48_MMR_DRAMSTS 0xFFCFA0EC
> +#define IO48_MMR_NIOS2_RESERVE0  0xFFCFA110
> +#define IO48_MMR_NIOS2_RESERVE1  0xFFCFA114
> +#define IO48_MMR_NIOS2_RESERVE2  0xFFCFA118
> +
> +#define SEQ2CORE_MASK0xF
> +#define CORE2SEQ_INT_REQ 0xF
> +#define SEQ2CORE_INT_RESP_BIT3
> +
> +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
> + (void *)SOCFPGA_SDR_ADDRESS;
> +static const struct socfpga_noc_ddr_scheduler 
> *socfpga_noc_ddr_scheduler_base =
> + (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
> + *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
> + (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
> + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
> +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
> + (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
> +
> +/* The followring are the supported configurations */
> +static u32 ddr_config[] = {
> + /* Chip - Row - Bank - Column Style */
> + /* All Types */
> + ARRIA_DDR_CONFIG(0, 3, 10, 12),
> + ARRIA_DDR_CONFIG(0, 3, 10, 13),
> + ARRIA_DDR_CONFIG(0, 3, 10, 14),
> + ARRIA_DDR_CONFIG(0, 3, 10, 15),
> + ARRIA_DDR_CONFIG(0, 3, 10, 16),
> + 

[U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[tien . fong . chee]

From: Tien Fong Chee 

Add DDR driver suppport for Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
 drivers/ddr/altera/sdram_arria10.c | 735 +
 3 files changed, 839 insertions(+), 1 deletion(-)
 create mode 100644 drivers/ddr/altera/sdram_arria10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index 4a9754e..b833fc2 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -10,6 +10,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 1d7b7c1..7af9431 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015-2017 Intel Corporation 
+ * Copyright (C) 2017 Intel Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0
  */
@@ -8,6 +8,7 @@
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
u32 ip_rev_id;
@@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
u32 niosreserve1;
u32 niosreserve2;
 };
+
+union dramaddrw_reg {
+   struct {
+   u32 cfg_col_addr_width:5;
+   u32 cfg_row_addr_width:5;
+   u32 cfg_bank_addr_width:4;
+   u32 cfg_bank_group_addr_width:2;
+   u32 cfg_cs_addr_width:3;
+   u32 reserved:13;
+   };
+   u32 word;
+};
+
+union ctrlcfg0_reg {
+   struct {
+   u32 cfg_mem_type:4;
+   u32 cfg_dimm_type:3;
+   u32 cfg_ac_pos:2;
+   u32 cfg_ctrl_burst_len:5;
+   u32 reserved:18;  /* Other fields unused */
+   };
+   u32 word;
+};
+
+union ctrlcfg1_reg {
+   struct {
+   u32 cfg_dbc3_burst_len:5;
+   u32 cfg_addr_order:2;
+   u32 cfg_ctrl_enable_ecc:1;
+   u32 reserved:24;  /* Other fields unused */
+   };
+   u32 word;
+};
+
+union caltiming0_reg {
+   struct {
+   u32 cfg_act_to_rdwr:6;
+   u32 cfg_act_to_pch:6;
+   u32 cfg_act_to_act:6;
+   u32 cfg_act_to_act_db:6;
+   u32 reserved:8;  /* Other fields unused */
+   };
+   u32 word;
+};
+
+union caltiming1_reg {
+   struct {
+   u32 cfg_rd_to_rd:6;
+   u32 cfg_rd_to_rd_dc:6;
+   u32 cfg_rd_to_rd_db:6;
+   u32 cfg_rd_to_wr:6;
+   u32 cfg_rd_to_wr_dc:6;
+   u32 reserved:2;
+   };
+   u32 word;
+};
+
+union caltiming2_reg {
+   struct {
+   u32 cfg_rd_to_wr_db:6;
+   u32 cfg_rd_to_pch:6;
+   u32 cfg_rd_ap_to_valid:6;
+   u32 cfg_wr_to_wr:6;
+   u32 cfg_wr_to_wr_dc:6;
+   u32 reserved:2;
+   };
+   u32 word;
+};
+
+union caltiming3_reg {
+   struct {
+   u32 cfg_wr_to_wr_db:6;
+   u32 cfg_wr_to_rd:6;
+   u32 cfg_wr_to_rd_dc:6;
+   u32 cfg_wr_to_rd_db:6;
+   u32 cfg_wr_to_pch:6;
+   u32 reserved:2;
+   };
+   u32 word;
+};
+
+union caltiming4_reg {
+   struct {
+   u32 cfg_wr_ap_to_valid:6;
+   u32 cfg_pch_to_valid:6;
+   u32 cfg_pch_all_to_valid:6;
+   u32 cfg_arf_to_valid:8;
+   u32 cfg_pdn_to_valid:6;
+   };
+   u32 word;
+};
+
+union caltiming9_reg {
+   struct {
+   u32 cfg_4_act_to_act:8;
+   u32 reserved:24;
+   };
+   u32 word;
+};
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK0x1F00
diff --git a/drivers/ddr/altera/sdram_arria10.c 
b/drivers/ddr/altera/sdram_arria10.c
new file mode 100644
index 000..f22a726
--- /dev/null
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -0,0 +1,735 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static unsigned long long sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK   (0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R)   ((A<<24)|(B<<16)|(C<<8)|R)
+#define DDR_CONFIG_ELEMENTS(sizeof(ddr_config)/sizeof(u32))
+#define DDR_REG_SEQ2CORE0xFFD0507C
+#define DDR_REG_CORE2SEQ