Re: [U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of outstanding read transactions for slave interface S2

[prabha...@freescale.com]

 -Original Message-
 From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Alison
 Wang
 Sent: Thursday, March 12, 2015 9:02 AM
 To: Sun York-R58495; u-boot@lists.denx.de; Jin Zhengxiong-R64188
 Subject: [U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of
 outstanding read transactions for slave interface S2
 

Patch subject is too long. Please try to make it = 78 charecters. 

 This patch will enable regulation of outstanding read transactions for slave
 interface S2 for silicon VER1.0.
 

It is already a patch. So please avoid  This patch

--prabhakar
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[U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of outstanding read transactions for slave interface S2

[Alison Wang]

This patch will enable regulation of outstanding read
transactions for slave interface S2 for silicon VER1.0.

Signed-off-by: Alison Wang alison.w...@freescale.com
---
Changes in v2:
- Modify the subject and commit to describe accurately

 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
 board/freescale/ls1021aqds/ls1021aqds.c   | 7 +++
 board/freescale/ls1021atwr/ls1021atwr.c   | 7 +++
 3 files changed, 16 insertions(+)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index a8122c1..1766f88 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -499,6 +499,8 @@ struct ccsr_ddr {
 #define CCI400_SHAORD_NON_SHAREABLE0x0002
 #define CCI400_DVM_MESSAGE_REQ_EN  0x0002
 #define CCI400_SNOOP_REQ_EN0x0001
+#define CCI400_REGULATION_READ_EN  0x0008
+#define CCI400_INT_MAX_OUT_TRANS   0x0100
 
 /* CCI-400 registers */
 struct ccsr_cci400 {
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index 69a5671..b7d1c90 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -225,6 +225,13 @@ int board_early_init_f(void)
 */
out_le32(cci-slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
out_le32(cci-slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+   /*
+* To fix interleaving issue on VER1.0, regulation of
+* outstanding read transactions for slave interface S2
+* is enabled
+*/
+   out_le32(cci-slave[2].qos_ctrl, CCI400_REGULATION_READ_EN);
+   out_le32(cci-slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS);
 
/* Workaround for the issue that DDR could not respond to
 * barrier transaction which is generated by executing DSB/ISB
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c 
b/board/freescale/ls1021atwr/ls1021atwr.c
index a9c87f2..bba3073 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -309,6 +309,13 @@ int board_early_init_f(void)
 */
out_le32(cci-slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
out_le32(cci-slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+   /*
+* To fix interleaving issue on VER1.0, regulation of
+* outstanding read transactions for slave interface S2
+* is enabled
+*/
+   out_le32(cci-slave[2].qos_ctrl, CCI400_REGULATION_READ_EN);
+   out_le32(cci-slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS);
}
 
return 0;
-- 
2.1.0.27.g96db324

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