Re: [U-Boot] [PATCH v2 3/3] rockchip: rk3036: clean mask definition for grf reg

2017-05-23 Thread sjg
On 15 May 2017 at 06:52, Kever Yang  wrote:
> U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
> definition in grf header file and pinctrl driver.
>
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v2:
> - add grf code clean
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 133 
> 
>  drivers/pinctrl/rockchip/pinctrl_rk3036.c   |  44 +++-
>  2 files changed, 82 insertions(+), 95 deletions(-)
>

Reviewed-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v2 3/3] rockchip: rk3036: clean mask definition for grf reg

2017-05-16 Thread Simon Glass
On 15 May 2017 at 06:52, Kever Yang  wrote:
> U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
> definition in grf header file and pinctrl driver.
>
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v2:
> - add grf code clean
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 133 
> 
>  drivers/pinctrl/rockchip/pinctrl_rk3036.c   |  44 +++-
>  2 files changed, 82 insertions(+), 95 deletions(-)
>

Reviewed-by: Simon Glass 
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[U-Boot] [PATCH v2 3/3] rockchip: rk3036: clean mask definition for grf reg

2017-05-15 Thread Kever Yang
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
definition in grf header file and pinctrl driver.

Signed-off-by: Kever Yang 
---

Changes in v2:
- add grf code clean

 arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 133 
 drivers/pinctrl/rockchip/pinctrl_rk3036.c   |  44 +++-
 2 files changed, 82 insertions(+), 95 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
index 72d133c..7625f24 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
@@ -83,57 +83,56 @@ check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
 /* GRF_GPIO0A_IOMUX */
 enum {
GPIO0A3_SHIFT   = 6,
-   GPIO0A3_MASK= 1,
+   GPIO0A3_MASK= 1 << GPIO0A3_SHIFT,
GPIO0A3_GPIO= 0,
GPIO0A3_I2C1_SDA,
 
GPIO0A2_SHIFT   = 4,
-   GPIO0A2_MASK= 1,
+   GPIO0A2_MASK= 1 << GPIO0A2_SHIFT,
GPIO0A2_GPIO= 0,
GPIO0A2_I2C1_SCL,
 
GPIO0A1_SHIFT   = 2,
-   GPIO0A1_MASK= 3,
+   GPIO0A1_MASK= 3 << GPIO0A1_SHIFT,
GPIO0A1_GPIO= 0,
GPIO0A1_I2C0_SDA,
GPIO0A1_PWM2,
 
GPIO0A0_SHIFT   = 0,
-   GPIO0A0_MASK= 3,
+   GPIO0A0_MASK= 3 << GPIO0A0_SHIFT,
GPIO0A0_GPIO= 0,
GPIO0A0_I2C0_SCL,
GPIO0A0_PWM1,
-
 };
 
 /* GRF_GPIO0B_IOMUX */
 enum {
GPIO0B6_SHIFT   = 12,
-   GPIO0B6_MASK= 3,
+   GPIO0B6_MASK= 3 << GPIO0B6_SHIFT,
GPIO0B6_GPIO= 0,
GPIO0B6_MMC1_D3,
GPIO0B6_I2S1_SCLK,
 
GPIO0B5_SHIFT   = 10,
-   GPIO0B5_MASK= 3,
+   GPIO0B5_MASK= 3 << GPIO0B5_SHIFT,
GPIO0B5_GPIO= 0,
GPIO0B5_MMC1_D2,
GPIO0B5_I2S1_SDI,
 
GPIO0B4_SHIFT   = 8,
-   GPIO0B4_MASK= 3,
+   GPIO0B4_MASK= 3 << GPIO0B4_SHIFT,
GPIO0B4_GPIO= 0,
GPIO0B4_MMC1_D1,
GPIO0B4_I2S1_LRCKTX,
 
GPIO0B3_SHIFT   = 6,
-   GPIO0B3_MASK= 3,
+   GPIO0B3_MASK= 3 << GPIO0B3_SHIFT,
GPIO0B3_GPIO= 0,
GPIO0B3_MMC1_D0,
GPIO0B3_I2S1_LRCKRX,
 
GPIO0B1_SHIFT   = 2,
-   GPIO0B1_MASK= 3,
+   GPIO0B1_MASK= 3 << GPIO0B1_SHIFT,
GPIO0B1_GPIO= 0,
GPIO0B1_MMC1_CLKOUT,
GPIO0B1_I2S1_MCLK,
@@ -148,28 +147,28 @@ enum {
 /* GRF_GPIO0C_IOMUX */
 enum {
GPIO0C4_SHIFT   = 8,
-   GPIO0C4_MASK= 1,
+   GPIO0C4_MASK= 1 << GPIO0C4_SHIFT,
GPIO0C4_GPIO= 0,
GPIO0C4_DRIVE_VBUS,
 
GPIO0C3_SHIFT   = 6,
-   GPIO0C3_MASK= 1,
+   GPIO0C3_MASK= 1 << GPIO0C3_SHIFT,
GPIO0C3_GPIO= 0,
GPIO0C3_UART0_CTSN,
 
GPIO0C2_SHIFT   = 4,
-   GPIO0C2_MASK= 1,
+   GPIO0C2_MASK= 1 << GPIO0C2_SHIFT,
GPIO0C2_GPIO= 0,
GPIO0C2_UART0_RTSN,
 
GPIO0C1_SHIFT   = 2,
-   GPIO0C1_MASK= 1,
+   GPIO0C1_MASK= 1 << GPIO0C1_SHIFT,
GPIO0C1_GPIO= 0,
GPIO0C1_UART0_SIN,
 
 
GPIO0C0_SHIFT   = 0,
-   GPIO0C0_MASK= 1,
+   GPIO0C0_MASK= 1 << GPIO0C0_SHIFT,
GPIO0C0_GPIO= 0,
GPIO0C0_UART0_SOUT,
 };
@@ -177,17 +176,17 @@ enum {
 /* GRF_GPIO0D_IOMUX */
 enum {
GPIO0D4_SHIFT   = 8,
-   GPIO0D4_MASK= 1,
+   GPIO0D4_MASK= 1 << GPIO0D4_SHIFT,
GPIO0D4_GPIO= 0,
GPIO0D4_SPDIF,
 
GPIO0D3_SHIFT   = 6,
-   GPIO0D3_MASK= 1,
+   GPIO0D3_MASK= 1 << GPIO0D3_SHIFT,
GPIO0D3_GPIO= 0,
GPIO0D3_PWM3,
 
GPIO0D2_SHIFT   = 4,
-   GPIO0D2_MASK= 1,
+   GPIO0D2_MASK= 1 << GPIO0D2_SHIFT,
GPIO0D2_GPIO= 0,
GPIO0D2_PWM0,
 };
@@ -195,33 +194,33 @@ enum {
 /* GRF_GPIO1A_IOMUX */
 enum {
GPIO1A5_SHIFT   = 10,
-   GPIO1A5_MASK= 1,
+   GPIO1A5_MASK= 1 << GPIO1A5_SHIFT,
GPIO1A5_GPIO= 0,
GPIO1A5_I2S_SDI,
 
GPIO1A4_SHIFT   = 8,
-   GPIO1A4_MASK= 1,
+   GPIO1A4_MASK= 1 << GPIO1A4_SHIFT,
GPIO1A4_GPIO= 0,
GPIO1A4_I2S_SD0,
 
GPIO1A3_SHIFT   = 6,
-   GPIO1A3_MASK= 1,
+   GPIO1A3_MASK= 1 << GPIO1A3_SHIFT,
GPIO1A3_GPIO= 0,
GPIO1A3_I2S_LRCKTX,