From: Manjunath Hadli <manjunath.ha...@ti.com>
add support for dm365 in speed.c file to use appropriate
PLL clocks to calculate cpu frequency and print.
Signed-off-by: sugumar <sugu...@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.ha...@ti.com>
---
arch/arm/cpu/arm926ejs/davinci/speed.c | 43 +++++++++++++++++++++++++++----
1 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c
b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 8c570ca..d1f227c 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -51,6 +51,13 @@
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
+#ifdef CONFIG_SOC_DM365
+#define ARM_PLLDIV PLLC_PLLDIV2
+#define DDR_PLLDIV PLLC_PLLDIV7
+#define SYSTEM_MOD 0x01C40000
+#define PERL_CTRL 0x48
+#endif
+
#ifdef CONFIG_SOC_DM644X
#define ARM_PLLDIV PLLC_PLLDIV2
#define DSP_PLLDIV PLLC_PLLDIV1
@@ -136,13 +143,15 @@ static inline unsigned pll_prediv(unsigned pllbase)
return 8;
else
return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+ return pll_div(pllbase, PLLC_PREDIV);
#endif
return 1;
}
static inline unsigned pll_postdiv(unsigned pllbase)
{
-#ifdef CONFIG_SOC_DM355
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
return pll_div(pllbase, PLLC_POSTDIV);
#elif defined(CONFIG_SOC_DM6446)
if (pllbase == DAVINCI_PLL_CNTRL0_BASE)
@@ -162,7 +171,11 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned
div)
/* the PLL might be bypassed */
if (readl(pll_addr + PLLC_PLLCTL) & BIT(0)) {
base /= pll_prediv(pll_addr);
- base *= 1 + (readl(pll_addr + PLLC_PLLM) & 0x0ff);
+#ifdef CONFIG_SOC_DM365
+ base *= (2 * (readl(pll_addr + PLLC_PLLM) & 0x3ff));
+#else
+ base *= (1 + (readl(pll_addr + PLLC_PLLM) & 0x0ff));
+#endif
base /= pll_postdiv(pll_addr);
}
return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
@@ -181,20 +194,38 @@ int showclocks(cmd_tbl_t *cmdtp,
/* REVISIT fetch and display CPU ID and revision information
* too ... that will matter as more revisions appear.
*/
+ unsigned int pllbase;
+ unsigned int sysdiv;
+
printf("Clock configuration:\n");
- printf("Cores: ARM %d MHz",
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+ pllbase = DAVINCI_PLL_CNTRL0_BASE;
+ sysdiv = ARM_PLLDIV;
+#ifdef CONFIG_SOC_DM365
+ pllbase = (readl(SYSTEM_MOD + PERL_CTRL) & BIT(29)) ?
+ DAVINCI_PLL_CNTRL1_BASE : DAVINCI_PLL_CNTRL0_BASE;
+#endif
+
+ printf("Cores: ARM %d MHz", pll_sysclk_mhz(pllbase, sysdiv));
#ifdef DSP_PLLDIV
printf(", DSP %d MHz",
pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
#endif
+ pllbase = DAVINCI_PLL_CNTRL1_BASE;
+ sysdiv = DDR_PLLDIV;
+#ifdef CONFIG_SOC_DM365
+ pllbase = (readl(SYSTEM_MOD + PERL_CTRL) & BIT(27)) ?
+ DAVINCI_PLL_CNTRL1_BASE : DAVINCI_PLL_CNTRL0_BASE;
+
+ if (pllbase == DAVINCI_PLL_CNTRL1_BASE)
+ sysdiv = PLLC_PLLDIV3;
+#endif
+
printf("\nDDR: %d MHz\n",
/* DDR PHY uses an x2 input clock */
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
- / 2);
+ pll_sysclk_mhz(pllbase, sysdiv) / 2);
return 0;
}
--
1.6.2.4
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