Re: [U-Boot] [PATCH v2 4/5] x86: coreboot: Control I/O port 0xb2 writing via device tree

2015-06-04 Thread Simon Glass
On 4 June 2015 at 02:47, Simon Glass s...@chromium.org wrote:
 On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
 Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
 U-Boot to hang on QEMU q35 target. We introduce a config option in the
 device tree u-boot,no-apm-finalize under /config node if we don't want
 to do that.

 Signed-off-by: Bin Meng bmeng...@gmail.com

 ---

 Changes in v2:
 - Use a config option in the device tree instead of deleting the codes

  arch/x86/cpu/coreboot/coreboot.c | 12 +---
  arch/x86/dts/qemu-x86_q35.dts|  1 +
  2 files changed, 10 insertions(+), 3 deletions(-)


 Acked-by: Simon Glass s...@chromium.org

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH v2 4/5] x86: coreboot: Control I/O port 0xb2 writing via device tree

2015-06-04 Thread Simon Glass
On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
 Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
 U-Boot to hang on QEMU q35 target. We introduce a config option in the
 device tree u-boot,no-apm-finalize under /config node if we don't want
 to do that.

 Signed-off-by: Bin Meng bmeng...@gmail.com

 ---

 Changes in v2:
 - Use a config option in the device tree instead of deleting the codes

  arch/x86/cpu/coreboot/coreboot.c | 12 +---
  arch/x86/dts/qemu-x86_q35.dts|  1 +
  2 files changed, 10 insertions(+), 3 deletions(-)


Acked-by: Simon Glass s...@chromium.org
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[U-Boot] [PATCH v2 4/5] x86: coreboot: Control I/O port 0xb2 writing via device tree

2015-06-02 Thread Bin Meng
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree u-boot,no-apm-finalize under /config node if we don't want
to do that.

Signed-off-by: Bin Meng bmeng...@gmail.com

---

Changes in v2:
- Use a config option in the device tree instead of deleting the codes

 arch/x86/cpu/coreboot/coreboot.c | 12 +---
 arch/x86/dts/qemu-x86_q35.dts|  1 +
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index c3dfd28..c4cac04 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -7,6 +7,7 @@
  */
 
 #include common.h
+#include fdtdec.h
 #include netdev.h
 #include asm/io.h
 #include asm/msr.h
@@ -74,9 +75,14 @@ void board_final_cleanup(void)
mtrr_close(state);
}
 
-   /* Issue SMI to Coreboot to lock down ME and registers */
-   printf(Finalizing Coreboot\n);
-   outb(0xcb, 0xb2);
+   if (!fdtdec_get_config_bool(gd-fdt_blob, u-boot,no-apm-finalize)) {
+   /*
+* Issue SMI to coreboot to lock down ME and registers
+* when allowed via device tree
+*/
+   printf(Finalizing coreboot\n);
+   outb(0xcb, 0xb2);
+   }
 }
 
 int misc_init_r(void)
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 6c89283..02a483c 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -15,6 +15,7 @@
 
config {
silent_console = 0;
+   u-boot,no-apm-finalize;
};
 
chosen {
-- 
1.8.2.1

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