Re: [U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
On Mon, Jun 29, 2015 at 5:06 AM, Peng Fan b51...@freescale.com wrote: Get you. I saw the code in gw_ventana.c to detect the DTB at runtime. I would suggest using the approach done at mx6cuboxi to detect the DTB at runtime: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=205d58699b157df75f1aa0b363ea9c21add21a0c;hp=6a305f22c58b5cef595b2e004fc6b299934dd82a Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
On Mon, Jun 29, 2015 at 09:02:20AM -0300, Fabio Estevam wrote: On Mon, Jun 29, 2015 at 5:06 AM, Peng Fan b51...@freescale.com wrote: Get you. I saw the code in gw_ventana.c to detect the DTB at runtime. I would suggest using the approach done at mx6cuboxi to detect the DTB at runtime: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=205d58699b157df75f1aa0b363ea9c21add21a0c;hp=6a305f22c58b5cef595b2e004fc6b299934dd82a Fabio, Thanks, good suggestion. Regards, Fabio Estevam Regards, Peng. -- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Hi Peng, On 29/06/2015 10:06, Peng Fan wrote: There is an important goal: having a single U-Boot image running on boards that can have different (pin compatible) SOCs. We get this managing the different layout of the IOMUXC, that was maybe the most difficult part - why do we go back when we can't ? Get you. I saw the code in gw_ventana.c to detect the DTB at runtime. To imx6q/qp/dl sabreauto board, there is no place to store info such as ventana_board_info. But this is a good point that gw_ventana use the way to do runtime check, which can make one image goal for pin compatible SOCs. Right - and this will be appreciate by sabreauto customers, who should not deal with several U-Boot images. And maybe asking why board is not booting after installing the wrong one. To the i.mx6qp board patch, I can use this way to remove the DTB related #ifdefs, use the way that gw_ventana uses. Will split the current patch into two, one to refacotr the current code to use runtime DTB detect, the second one is to add i.mx6qp support. It looks like a nice plan ;-). Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Hi Stefano,
On Mon, Jun 29, 2015 at 09:26:10AM +0200, Stefano Babic wrote:
Hi Peng,
On 29/06/2015 04:05, Peng Fan wrote:
To be sure I have not misunderstood the other patches: this is ok and
this is what I am expecting. Code checks the SOC and provides a
different action for QP or Quad or..
But if some parts are defined at compile time, the check is losing its
original meaning and the behavior is already defined at build time.
is_mx6dqp is runtime checking, it's behavior is not defined at build time.
There are some places which has the macro, #ifdef CONFIG_MX6QP, but all in
header files, not in xx.c files.
Exactly, this is what I mean - here there is a runtime check, but this
can be vanified by some #ifdef in header.
The same here
Since this is board header files, different SOCs needs different dtbs.
The behavior is defined at build time.
You're wrong. We accepted some code to detect at runtime which is the
correct DTB to be selected. In fact, one goal is to have a single kernel
as image, using the correct DTB to select the hardware.
This work if we have the same U-Boot is running on different SOC
variants. If U-Boot is hardcoded, why do we need to detect the right DTB
? It could be also hard-coded.
I think it is not good to add
such piece of code in board file:
int board_late_init()
{
if (is_mx6dqp())
setenv(fdt_file, imx6qp-sabreauto.dtb) /* Just an example */
It must be checked if fdt_file is already set, because the customer can
decide to use its own, but well, yes, this is done by other boards -
check in code.
}
So I prefer to use #if defined CONFIG_MX6QP in board header file.
There is an important goal: having a single U-Boot image running on
boards that can have different (pin compatible) SOCs. We get this
managing the different layout of the IOMUXC, that was maybe the most
difficult part - why do we go back when we can't ?
Get you.
I saw the code in gw_ventana.c to detect the DTB at runtime.
To imx6q/qp/dl sabreauto board, there is no place to store info such as
ventana_board_info. But this is a good point that gw_ventana use the way
to do runtime check, which can make one image goal for pin compatible SOCs.
To the i.mx6qp board patch, I can use this way to remove the
DTB related #ifdefs, use the way that gw_ventana uses. Will split the current
patch into two, one to refacotr the current code to use runtime DTB detect,
the second one is to add i.mx6qp support.
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
Regards,
Peng.
--
___
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Re: [U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Hi Peng,
On 29/06/2015 04:05, Peng Fan wrote:
To be sure I have not misunderstood the other patches: this is ok and
this is what I am expecting. Code checks the SOC and provides a
different action for QP or Quad or..
But if some parts are defined at compile time, the check is losing its
original meaning and the behavior is already defined at build time.
is_mx6dqp is runtime checking, it's behavior is not defined at build time.
There are some places which has the macro, #ifdef CONFIG_MX6QP, but all in
header files, not in xx.c files.
Exactly, this is what I mean - here there is a runtime check, but this
can be vanified by some #ifdef in header.
The same here
Since this is board header files, different SOCs needs different dtbs.
The behavior is defined at build time.
You're wrong. We accepted some code to detect at runtime which is the
correct DTB to be selected. In fact, one goal is to have a single kernel
as image, using the correct DTB to select the hardware.
This work if we have the same U-Boot is running on different SOC
variants. If U-Boot is hardcoded, why do we need to detect the right DTB
? It could be also hard-coded.
I think it is not good to add
such piece of code in board file:
int board_late_init()
{
if (is_mx6dqp())
setenv(fdt_file, imx6qp-sabreauto.dtb) /* Just an example */
It must be checked if fdt_file is already set, because the customer can
decide to use its own, but well, yes, this is done by other boards -
check in code.
}
So I prefer to use #if defined CONFIG_MX6QP in board header file.
There is an important goal: having a single U-Boot image running on
boards that can have different (pin compatible) SOCs. We get this
managing the different layout of the IOMUXC, that was maybe the most
difficult part - why do we go back when we can't ?
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
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Re: [U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Hi Stefano, On Sat, Jun 27, 2015 at 07:08:14PM +0200, Stefano Babic wrote: Hi Peng, On 11/06/2015 12:30, Peng Fan wrote: 1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800) CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 26C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 4096 MiB MMC: FSL_SDHC: 0 No panel detected: default to HDMI Display: HDMI (1024x768) In:serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Robin Gong b38...@freescale.com Signed-off-by: Ye.Li b37...@freescale.com Signed-off-by: Peng Fan peng@freescale.com --- Changes v2: 1. Remove unused macro in current upstream uboot. 2. setup_fec, remove non 6qp code. Add comments for gpr setting. 3. mx6qp.cfg is still same with v1. The settings is from IC and passed memory ddr stress test. Since we current have no plan to add SPL, so leave settings unchanged. board/freescale/mx6qsabreauto/mx6qp.cfg | 143 ++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 29 -- configs/mx6qpsabreauto_defconfig | 5 + include/configs/mx6qsabreauto.h | 5 +- 4 files changed, 175 insertions(+), 7 deletions(-) create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg create mode 100644 configs/mx6qpsabreauto_defconfig diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg new file mode 100644 index 000..0370636 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6qp.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +#define __ASSEMBLY__ +#include config.h + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C +DATA 4 0x020e0758 0x +DATA 4 0x020e0588 0x0030 +DATA 4 0x020e0594 0x0030 +DATA 4 0x020e056c 0x0030 +DATA 4 0x020e0578 0x0030 +DATA 4 0x020e074c 0x0030 +DATA 4 0x020e057c 0x0030 +DATA 4 0x020e058c 0x +DATA 4 0x020e059c 0x0030 +DATA 4 0x020e05a0 0x0030 +DATA 4 0x020e078c 0x0030 +DATA 4 0x020e0750 0x0002 +DATA 4 0x020e05a8 0x0030 +DATA 4 0x020e05b0 0x0030 +DATA 4 0x020e0524 0x0030 +DATA 4 0x020e051c 0x0030 +DATA 4 0x020e0518 0x0030 +DATA 4 0x020e050c 0x0030 +DATA 4 0x020e05b8 0x0030 +DATA 4 0x020e05c0 0x0030 +DATA 4 0x020e0774 0x0002 +DATA 4 0x020e0784 0x0030 +DATA 4 0x020e0788 0x0030 +DATA 4 0x020e0794 0x0030 +DATA 4 0x020e079c 0x0030 +DATA 4 0x020e07a0 0x0030 +DATA 4 0x020e07a4 0x0030 +DATA 4 0x020e07a8 0x0030 +DATA 4 0x020e0748 0x0030 +DATA 4 0x020e05ac 0x0030 +DATA 4 0x020e05b4 0x0030 +DATA 4 0x020e0528 0x0030 +DATA 4 0x020e0520 0x0030 +DATA 4 0x020e0514 0x0030 +DATA 4 0x020e0510 0x0030 +DATA 4 0x020e05bc 0x0030 +DATA 4 0x020e05c4 0x0030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x +DATA 4 0x021b0820 0x +DATA 4 0x021b0824 0x +DATA 4 0x021b0828 0x +DATA 4 0x021b481c 0x +DATA 4 0x021b4820 0x +DATA 4 0x021b4824 0x +DATA 4 0x021b4828 0x +DATA 4 0x021b08b8 0x0800 +DATA 4 0x021b48b8 0x0800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA
Re: [U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Hi Peng, On 11/06/2015 12:30, Peng Fan wrote: 1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800) CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 26C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 4096 MiB MMC: FSL_SDHC: 0 No panel detected: default to HDMI Display: HDMI (1024x768) In:serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Robin Gong b38...@freescale.com Signed-off-by: Ye.Li b37...@freescale.com Signed-off-by: Peng Fan peng@freescale.com --- Changes v2: 1. Remove unused macro in current upstream uboot. 2. setup_fec, remove non 6qp code. Add comments for gpr setting. 3. mx6qp.cfg is still same with v1. The settings is from IC and passed memory ddr stress test. Since we current have no plan to add SPL, so leave settings unchanged. board/freescale/mx6qsabreauto/mx6qp.cfg | 143 ++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 29 -- configs/mx6qpsabreauto_defconfig | 5 + include/configs/mx6qsabreauto.h | 5 +- 4 files changed, 175 insertions(+), 7 deletions(-) create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg create mode 100644 configs/mx6qpsabreauto_defconfig diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg new file mode 100644 index 000..0370636 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6qp.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +#define __ASSEMBLY__ +#include config.h + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ +BOOT_FROMsd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C +DATA 4 0x020e0758 0x +DATA 4 0x020e0588 0x0030 +DATA 4 0x020e0594 0x0030 +DATA 4 0x020e056c 0x0030 +DATA 4 0x020e0578 0x0030 +DATA 4 0x020e074c 0x0030 +DATA 4 0x020e057c 0x0030 +DATA 4 0x020e058c 0x +DATA 4 0x020e059c 0x0030 +DATA 4 0x020e05a0 0x0030 +DATA 4 0x020e078c 0x0030 +DATA 4 0x020e0750 0x0002 +DATA 4 0x020e05a8 0x0030 +DATA 4 0x020e05b0 0x0030 +DATA 4 0x020e0524 0x0030 +DATA 4 0x020e051c 0x0030 +DATA 4 0x020e0518 0x0030 +DATA 4 0x020e050c 0x0030 +DATA 4 0x020e05b8 0x0030 +DATA 4 0x020e05c0 0x0030 +DATA 4 0x020e0774 0x0002 +DATA 4 0x020e0784 0x0030 +DATA 4 0x020e0788 0x0030 +DATA 4 0x020e0794 0x0030 +DATA 4 0x020e079c 0x0030 +DATA 4 0x020e07a0 0x0030 +DATA 4 0x020e07a4 0x0030 +DATA 4 0x020e07a8 0x0030 +DATA 4 0x020e0748 0x0030 +DATA 4 0x020e05ac 0x0030 +DATA 4 0x020e05b4 0x0030 +DATA 4 0x020e0528 0x0030 +DATA 4 0x020e0520 0x0030 +DATA 4 0x020e0514 0x0030 +DATA 4 0x020e0510 0x0030 +DATA 4 0x020e05bc 0x0030 +DATA 4 0x020e05c4 0x0030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x +DATA 4 0x021b0820 0x +DATA 4 0x021b0824 0x +DATA 4 0x021b0828 0x +DATA 4 0x021b481c 0x +DATA 4 0x021b4820 0x +DATA 4 0x021b4824 0x +DATA 4 0x021b4828 0x +DATA 4 0x021b08b8 0x0800 +DATA 4 0x021b48b8 0x0800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x1740 +DATA 4 0x021b001c 0x8000 + +DATA 4
Re: [U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Hi Peng, On Thu, Jun 11, 2015 at 7:30 AM, Peng Fan peng@freescale.com wrote: 1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800) CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz) Please make it to display i.MX6QP instead. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800) CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 26C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 4096 MiB MMC: FSL_SDHC: 0 No panel detected: default to HDMI Display: HDMI (1024x768) In:serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Robin Gong b38...@freescale.com Signed-off-by: Ye.Li b37...@freescale.com Signed-off-by: Peng Fan peng@freescale.com --- Changes v2: 1. Remove unused macro in current upstream uboot. 2. setup_fec, remove non 6qp code. Add comments for gpr setting. 3. mx6qp.cfg is still same with v1. The settings is from IC and passed memory ddr stress test. Since we current have no plan to add SPL, so leave settings unchanged. board/freescale/mx6qsabreauto/mx6qp.cfg | 143 ++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 29 -- configs/mx6qpsabreauto_defconfig | 5 + include/configs/mx6qsabreauto.h | 5 +- 4 files changed, 175 insertions(+), 7 deletions(-) create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg create mode 100644 configs/mx6qpsabreauto_defconfig diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg new file mode 100644 index 000..0370636 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6qp.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +#define __ASSEMBLY__ +#include config.h + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C +DATA 4 0x020e0758 0x +DATA 4 0x020e0588 0x0030 +DATA 4 0x020e0594 0x0030 +DATA 4 0x020e056c 0x0030 +DATA 4 0x020e0578 0x0030 +DATA 4 0x020e074c 0x0030 +DATA 4 0x020e057c 0x0030 +DATA 4 0x020e058c 0x +DATA 4 0x020e059c 0x0030 +DATA 4 0x020e05a0 0x0030 +DATA 4 0x020e078c 0x0030 +DATA 4 0x020e0750 0x0002 +DATA 4 0x020e05a8 0x0030 +DATA 4 0x020e05b0 0x0030 +DATA 4 0x020e0524 0x0030 +DATA 4 0x020e051c 0x0030 +DATA 4 0x020e0518 0x0030 +DATA 4 0x020e050c 0x0030 +DATA 4 0x020e05b8 0x0030 +DATA 4 0x020e05c0 0x0030 +DATA 4 0x020e0774 0x0002 +DATA 4 0x020e0784 0x0030 +DATA 4 0x020e0788 0x0030 +DATA 4 0x020e0794 0x0030 +DATA 4 0x020e079c 0x0030 +DATA 4 0x020e07a0 0x0030 +DATA 4 0x020e07a4 0x0030 +DATA 4 0x020e07a8 0x0030 +DATA 4 0x020e0748 0x0030 +DATA 4 0x020e05ac 0x0030 +DATA 4 0x020e05b4 0x0030 +DATA 4 0x020e0528 0x0030 +DATA 4 0x020e0520 0x0030 +DATA 4 0x020e0514 0x0030 +DATA 4 0x020e0510 0x0030 +DATA 4 0x020e05bc 0x0030 +DATA 4 0x020e05c4 0x0030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x +DATA 4 0x021b0820 0x +DATA 4 0x021b0824 0x +DATA 4 0x021b0828 0x +DATA 4 0x021b481c 0x +DATA 4 0x021b4820 0x +DATA 4 0x021b4824 0x +DATA 4 0x021b4828 0x +DATA 4 0x021b08b8 0x0800 +DATA 4 0x021b48b8 0x0800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x1740 +DATA 4 0x021b001c 0x8000 + +DATA 4 0x021b002c 0x26d2 +DATA 4 0x021b0030 0x008E1023 +DATA 4 0x021b0040 0x0047 +DATA 4 0x021b0400 0x1242 +DATA 4 0x021b 0x841A +DATA 4 0x00bb0008 0x0004 +DATA 4 0x00bb000c 0x2891E41A
