Re: [U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
Hi
Thanks for feedback. PATVH v4 will coming soon. about 'CONFIG_SPL_FRAMEWORK'
I don't know this when I working on ben nanonote spl. I think I will stick
with this spl for awhile.
is there a plan remove drivers/mtd/nand/nand_spl_*.c?
Xiangfu
On 10/10/2012 05:27 AM, Daniel Schwierzeck wrote:
2012/10/9 Tom Rini tr...@ti.com:
On Tue, Oct 09, 2012 at 04:28:05PM +0800, xian...@openmobilefree.net wrote:
From: Xiangfu Liu xian...@openmobilefree.net
* After create u-boot-spl.bin. it needs those 4 commands create final
image for jz4740 cpu.
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync bs=8192 count=1
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync,notrunc
oflag=append bs=8192 count=1
tr '\0' '\377' /dev/zero | dd of=u-boot-nand.bin conv=sync,notrunc
oflag=append bs=16384 count=1
cat u-boot-nand.bin u-boot.bin u-boot-nand-final.bin
The JZ4740 CPU can load 8KB from two different addresses:
1. the normal area up to 8KB starting from NAND flash address 0x
2. the backup area up to 8KB starting from NAND flash address 0x2000
* Add software usbboot mode
Downloads user program from the USB port to internal
SRAM and branches to the internal SRAM to execute the program.
(JZ4740 CPU have a internal ROM have such kind of code, that make
JZ4740 can boot from USB)
---
v3:
* add simpile string.c to mips/lib
* some cleanup on jz4740.c
* move to new spl/ structure
* support software usbboot mode
I'm happy you've moved to the new SPL infrastructure. A few comments:
In general, please check for checkpatch.pl issues, I spotted a few.
Also, don't use // comments in asm, everything else in MIPS uses '#' or
'/* ... */'. Please use 'puts' rather than 'serial_puts' directly.
[snip]
diff --git a/arch/mips/lib/string.c b/arch/mips/lib/string.c
new file mode 100644
index 000..d59f44a
--- /dev/null
+++ b/arch/mips/lib/string.c
@@ -0,0 +1,32 @@
Can you try just enabling CONFIG_SPL_LIBGENERIC_SUPPORT ? You should
have the unused functions garbage collected automatically.
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..4ab2229 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -15,6 +15,9 @@
#include asm/io.h
#include asm/jz4740.h
+#ifdef CONFIG_SPL_BUILD
+#define printf(arg...) do {} while (0)
+#endif
In this case you should just switch to puts.
And a non-blocking question, have you looked at the CONFIG_SPL_FRAMEWORK
code in common/spl/ now?
in addition to Tom's comments:
please split coding style cleanups, code reordering, NAND SPL and USB
boot into separate patches
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Re: [U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
Hi Tom Rini I cannot easy find a way to use 'puts' instead 'serial_puts' in my code. any advise will be great. Thanks Xiangfu On 10/10/2012 05:27 AM, Daniel Schwierzeck wrote: I'm happy you've moved to the new SPL infrastructure. A few comments: In general, please check for checkpatch.pl issues, I spotted a few. Also, don't use // comments in asm, everything else in MIPS uses '#' or '/* ... */'. Please use 'puts' rather than 'serial_puts' directly. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 10/10/12 20:19, Xiangfu Liu wrote: Hi Tom Rini I cannot easy find a way to use 'puts' instead 'serial_puts' in my code. any advise will be great. You should be able to use CONFIG_SPL_LIBCOMMON_SUPPORT without CONFIG_SPL_FRAMEWORK and get 'puts'. - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://www.enigmail.net/ iQIcBAEBAgAGBQJQd0bGAAoJENk4IS6UOR1Wl6EP/ip/TVA/lLHYv+rcZuu8oJyZ fh5rYYaprLsIzt9esQ9lBjhxFsEvmofGYzFLyMR318Z2cyxTAdOYWLRD+JkFLZAJ nd5SB5Co8mKUBXxpnGN8k0dUT00G+dZvgYE1BM37uC+fLpaZXqrncn+4O4xU2GP/ tsbAXUG1K+KmEB8B1xKSrsrKU6CCfh8bbZZaj541mFRHcgjF+ZWIoWFoTR7HedgZ LLcY+LSMxXntK/P5jH8mq9feLU7fPqVo9jxUBlkF35IQTAI3+1X88tkwzObYD8az c2sRgACQh+pgoY2VA6t2YhUp+gFOiHxGUqr+xiFndQhKFs+LNsziNbT4ddptKTb7 3SZi8roOifxc1/K6vW7rxs5F5AOzYajstTDepgHCHeW/zks3NZq0qFNSZAK9GS/C Sh0Q9Uxo9FqW7LpXtSXTj9AUJ5TRD4pKZYcTEBETlZqqWfqTUMJkhV/KEEq0IxRR NJctAVYq5clDl/Jq12F5YygTpA7o7OCGT0EIPsTudpijbkjnEA7FT1F0Y6oQV6+z 0ibshUuty1FVcIJ/ccJPChPSQqFfXZqrf6SOiEU1exe4ap/nC0MtBOGhcs7lkYzr com4uYPPeVqogcLAxJwMTz/qaAzEdLWo09Qi4vLt2O/YUB9KHKy/9hyzMo63P2xM IkT2O2SxNONOZfhXlhMd =yBoD -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
From: Xiangfu Liu xian...@openmobilefree.net
* After create u-boot-spl.bin. it needs those 4 commands create final image
for jz4740 cpu.
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync bs=8192 count=1
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync,notrunc oflag=append
bs=8192 count=1
tr '\0' '\377' /dev/zero | dd of=u-boot-nand.bin conv=sync,notrunc
oflag=append bs=16384 count=1
cat u-boot-nand.bin u-boot.bin u-boot-nand-final.bin
The JZ4740 CPU can load 8KB from two different addresses:
1. the normal area up to 8KB starting from NAND flash address 0x
2. the backup area up to 8KB starting from NAND flash address 0x2000
* Add software usbboot mode
Downloads user program from the USB port to internal
SRAM and branches to the internal SRAM to execute the program.
(JZ4740 CPU have a internal ROM have such kind of code, that make
JZ4740 can boot from USB)
---
v3:
* add simpile string.c to mips/lib
* some cleanup on jz4740.c
* move to new spl/ structure
* support software usbboot mode
arch/mips/cpu/xburst/Makefile |7 +-
arch/mips/cpu/xburst/cpu.c|4 +
arch/mips/cpu/xburst/jz4740.c | 84 ++--
arch/mips/cpu/xburst/spl/Makefile | 47 ++
arch/mips/cpu/xburst/spl/start.S | 65 +++
arch/mips/lib/Makefile|4 +
arch/mips/lib/string.c| 32 ++
board/qi/qi_lb60/Makefile |5 +
board/qi/qi_lb60/qi_lb60-spl.c| 56 +++
board/qi/qi_lb60/qi_lb60.c|6 +-
board/qi/qi_lb60/u-boot-spl.lds | 62 +++
board/qi/qi_lb60/usbboot.S| 880 +
drivers/mtd/nand/jz4740_nand.c| 39 +-
include/configs/qi_lb60.h | 173
14 files changed, 1319 insertions(+), 145 deletions(-)
create mode 100644 arch/mips/cpu/xburst/spl/Makefile
create mode 100644 arch/mips/cpu/xburst/spl/start.S
create mode 100644 arch/mips/lib/string.c
create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
create mode 100644 board/qi/qi_lb60/usbboot.S
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
index b1f2ae4..ec35e55 100644
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
+COBJS-y= cpu.o jz_serial.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
START = start.o
-SOBJS-y=
-COBJS-y= cpu.o timer.o jz_serial.o
+COBJS-y += timer.o
+endif
COBJS-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..1432838 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: i (op), R (*(unsigned char *)(addr)))
+#ifndef CONFIG_SPL_BUILD
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
index c0b9817..40ef411 100644
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@@ -32,31 +32,19 @@ int disable_interrupts(void)
return 0;
}
-/*
- * PLL output clock = EXTAL * NF / (NR * NO)
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
void pll_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- register unsigned int cfcr, plcr1;
- int n2FR[33] = {
- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
- 9
- };
- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
- int nf, pllout2;
+ register unsigned int cfcr, plcr;
+ unsigned int nf, pllout2;
cfcr = CPM_CPCCR_CLKOEN |
- CPM_CPCCR_PCS |
- (n2FR[div[0]] CPM_CPCCR_CDIV_BIT) |
- (n2FR[div[1]] CPM_CPCCR_HDIV_BIT) |
- (n2FR[div[2]] CPM_CPCCR_PDIV_BIT) |
- (n2FR[div[3]] CPM_CPCCR_MDIV_BIT) |
- (n2FR[div[4]] CPM_CPCCR_LDIV_BIT);
+ (0 CPM_CPCCR_CDIV_BIT) |
+ (2 CPM_CPCCR_HDIV_BIT) |
+ (2 CPM_CPCCR_PDIV_BIT) |
+ (2 CPM_CPCCR_MDIV_BIT) |
+ (2 CPM_CPCCR_LDIV_BIT);
pllout2 = (cfcr CPM_CPCCR_PCS) ?
CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
@@ -65,15 +53,18 @@ void pll_init(void)
writel(pllout2 / 4800 - 1, cpm-uhccdr);
nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
- plcr1 = ((nf - 2) CPM_CPPCR_PLLM_BIT) | /* FD */
+ plcr = ((nf -
Re: [U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
2012/10/9 Tom Rini tr...@ti.com:
On Tue, Oct 09, 2012 at 04:28:05PM +0800, xian...@openmobilefree.net wrote:
From: Xiangfu Liu xian...@openmobilefree.net
* After create u-boot-spl.bin. it needs those 4 commands create final image
for jz4740 cpu.
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync bs=8192 count=1
dd if=spl/u-boot-spl.bin of=u-boot-nand.bin conv=sync,notrunc oflag=append
bs=8192 count=1
tr '\0' '\377' /dev/zero | dd of=u-boot-nand.bin conv=sync,notrunc
oflag=append bs=16384 count=1
cat u-boot-nand.bin u-boot.bin u-boot-nand-final.bin
The JZ4740 CPU can load 8KB from two different addresses:
1. the normal area up to 8KB starting from NAND flash address 0x
2. the backup area up to 8KB starting from NAND flash address 0x2000
* Add software usbboot mode
Downloads user program from the USB port to internal
SRAM and branches to the internal SRAM to execute the program.
(JZ4740 CPU have a internal ROM have such kind of code, that make
JZ4740 can boot from USB)
---
v3:
* add simpile string.c to mips/lib
* some cleanup on jz4740.c
* move to new spl/ structure
* support software usbboot mode
I'm happy you've moved to the new SPL infrastructure. A few comments:
In general, please check for checkpatch.pl issues, I spotted a few.
Also, don't use // comments in asm, everything else in MIPS uses '#' or
'/* ... */'. Please use 'puts' rather than 'serial_puts' directly.
[snip]
diff --git a/arch/mips/lib/string.c b/arch/mips/lib/string.c
new file mode 100644
index 000..d59f44a
--- /dev/null
+++ b/arch/mips/lib/string.c
@@ -0,0 +1,32 @@
Can you try just enabling CONFIG_SPL_LIBGENERIC_SUPPORT ? You should
have the unused functions garbage collected automatically.
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..4ab2229 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -15,6 +15,9 @@
#include asm/io.h
#include asm/jz4740.h
+#ifdef CONFIG_SPL_BUILD
+#define printf(arg...) do {} while (0)
+#endif
In this case you should just switch to puts.
And a non-blocking question, have you looked at the CONFIG_SPL_FRAMEWORK
code in common/spl/ now?
in addition to Tom's comments:
please split coding style cleanups, code reordering, NAND SPL and USB
boot into separate patches
--
Best regards,
Daniel
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Re: [U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
Dear Xiangfu Liu, In message 1326207993-17791-1-git-send-email-xian...@openmobilefree.net you wrote: Signed-off-by: Xiangfu Liu xian...@openmobilefree.net --- Changes for v2: -Add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -Cleanup jz4740_nand.c a little Changes for v3: -Remove CONFIG_NAND_SPL_TEXT_BASE, fix the wrong TEXT base under SPL u-boot.lds -Remove overcomplicated 'dd', pad to 32KB SPL instead of 256. comments added in Makefile -Cleanup the qi_lb60.h arch/mips/cpu/xburst/cpu.c |4 + arch/mips/cpu/xburst/start_spl.S | 65 + drivers/mtd/nand/jz4740_nand.c | 40 - include/configs/qi_lb60.h| 166 -- nand_spl/board/qi/qi_lb60/Makefile | 124 + nand_spl/board/qi/qi_lb60/nand_spl.c | 37 nand_spl/board/qi/qi_lb60/u-boot.lds | 62 + 7 files changed, 407 insertions(+), 91 deletions(-) create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 nand_spl/board/qi/qi_lb60/Makefile create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds I don't want to see more boards added to the old /nand_spl/ infrastructure. You said you were converting to /spl/ instead? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Die Scheu vor Verantwortung ist die Krankheit unserer Zeit. -- Otto von Bismarck ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board
Signed-off-by: Xiangfu Liu xian...@openmobilefree.net
---
Changes for v2:
-Add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-Cleanup jz4740_nand.c a little
Changes for v3:
-Remove CONFIG_NAND_SPL_TEXT_BASE, fix the wrong TEXT base under SPL u-boot.lds
-Remove overcomplicated 'dd', pad to 32KB SPL instead of 256. comments added
in Makefile
-Cleanup the qi_lb60.h
arch/mips/cpu/xburst/cpu.c |4 +
arch/mips/cpu/xburst/start_spl.S | 65 +
drivers/mtd/nand/jz4740_nand.c | 40 -
include/configs/qi_lb60.h| 166 --
nand_spl/board/qi/qi_lb60/Makefile | 124 +
nand_spl/board/qi/qi_lb60/nand_spl.c | 37
nand_spl/board/qi/qi_lb60/u-boot.lds | 62 +
7 files changed, 407 insertions(+), 91 deletions(-)
create mode 100644 arch/mips/cpu/xburst/start_spl.S
create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index e976341..afd166c 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
: \
: i (op), R (*(unsigned char *)(addr)))
+#ifndef CONFIG_NAND_SPL
+
void __attribute__((weak)) _machine_restart(void)
{
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
cache_op(Hit_Invalidate_D, addr);
}
+#endif
+
void flush_icache_all(void)
{
u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S
new file mode 100644
index 000..f137ccd
--- /dev/null
+++ b/arch/mips/cpu/xburst/start_spl.S
@@ -0,0 +1,65 @@
+/*
+ * Startup Code for MIPS32 XBURST CPU-core
+ *
+ * Copyright (c) 2010 Xiangfu Liu xian...@sharism.cc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include config.h
+#include version.h
+#include asm/regdef.h
+#include asm/mipsregs.h
+#include asm/addrspace.h
+#include asm/cacheops.h
+
+#include asm/jz4740.h
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
+reset:
+ /*
+* STATUS register
+* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
+*/
+ li t0, 0x0040FC04
+ mtc0t0, CP0_STATUS
+ /*
+* CAUSE register
+* IV=1, use the specical interrupt vector (0x200)
+*/
+ li t1, 0x0080
+ mtc0t1, CP0_CAUSE
+
+ bal 1f
+nop
+ .word _GLOBAL_OFFSET_TABLE_
+1:
+ movegp, ra
+ lw t1, 0(ra)
+ movegp, t1
+
+ la sp, 0x80004000
+ la t9, nand_spl_boot
+ j t9
+nop
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..7ef07a5 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -15,6 +15,10 @@
#include asm/io.h
#include asm/jz4740.h
+#ifdef CONFIG_NAND_SPL
+ #define printf(arg...) do {} while (0)
+#endif
+
#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB800)
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
@@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
for (k = 0; k 9; k++)
writeb(read_ecc[k], emc-nfpar[k]);
}
- /* Set PRDY */
+
writel(readl(emc-nfecr) | EMC_NFECR_PRDY, emc-nfecr);
/* Wait for completion */
@@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
status = readl(emc-nfints);
} while (!(status EMC_NFINTS_DECF));
- /* disable ecc */
+ /* Disable ECC */
writel(readl(emc-nfecr) ~EMC_NFECR_ECCE, emc-nfecr);
/* Check decoding */
@@ -192,7 +196,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd,
u_char *dat,
return 0;
if (status
