From: Sergey Kostanbaev
This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev
Cc: albert.u.b...@aribaud.net
---
Changes for v3:
- Update makefiles to the new style
Changes for v2:
- Replace constants in lowlevel_init.S to defines
- Add more coments in non-trivial places in lowlevel_init.S
- Get rid of ep93xx_sdram_find_bank in lowlevel_init.S and
move it to dram_fill_bank_addr in edb93xx.c. This procedure
may be executed later at any time, so no need to be in lowlevel
arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S | 465 ++--
arch/arm/include/asm/arch-ep93xx/ep93xx.h | 86 +
board/cirrus/edb93xx/Makefile | 37 +++
board/cirrus/edb93xx/edb93xx.c | 382 +++
board/cirrus/edb93xx/u-boot.lds | 106 +++
boards.cfg | 1 +
drivers/spi/Makefile| 1 +
drivers/spi/ep93xx_spi.c| 274
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ohci-ep93xx.c | 38 +++
include/configs/edb93xx.h | 292 +
11 files changed, 1654 insertions(+), 29 deletions(-)
create mode 100644 board/cirrus/edb93xx/Makefile
create mode 100644 board/cirrus/edb93xx/edb93xx.c
create mode 100644 board/cirrus/edb93xx/u-boot.lds
create mode 100644 drivers/spi/ep93xx_spi.c
create mode 100644 drivers/usb/host/ohci-ep93xx.c
create mode 100644 include/configs/edb93xx.h
diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
index bf2fa2a..3ac0f88 100644
--- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -1,49 +1,456 @@
/*
* Low-level initialization for EP93xx
*
- * Copyright (C) 2009 Matthias Kaehlcke
+ * Copyright (C) 2013
+ * Sergey Kostanabev fairwaves.ru>
*
- * Copyright (C) 2006 Dominic Rath
+ * Copyright (C) 2006 Cirrus Logic Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
*
* SPDX-License-Identifier:GPL-2.0+
*/
-#include
-#include
+#include
+#include
+
+/*
+/* Configure the SDRAM based on the supplied settings.
+ *
+ * Input: r0 - SDRAM DEVCFG register
+ * r2 - configuration for SDRAM chips
+ * Output: none
+ * Modifies: r3, r4
+ */
+ep93xx_sdram_config:
+ /* Program the SDRAM device configuration register. */
+ ldr r3, =SDRAM_BASE
+#ifdef CONFIG_EDB93XX_SDCS0
+ str r0, [r3, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+ str r0, [r3, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+ str r0, [r3, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+ str r0, [r3, #SDRAM_OFF_DEVCFG3]
+#endif
+
+ /* Set the Initialize and MRS bits (issue continuous NOP commands
+* (INIT & MRS set))
+*/
+ ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+ EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
+ EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+ str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+ /* Delay for 200us. */
+ mov r4, #0x3000
+delay1:
+ subsr4, r4, #1
+ bne delay1
+
+ /* Clear the MRS bit to issue a precharge all. */
+ ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+ EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+ str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+ /* Temporarily set the refresh timer to 0x10. Make it really low so
+* that refresh cycles are generated.
+*/
+ ldr r4, =0x10
+ str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+ /* Delay for at least 80 SDRAM clock cycles. */
+ mov r4, #80
+delay2:
+ subsr4, r4, #1
+ bne delay2
+
+ /* Set the refresh timer to the fastest required for any device
+* that might be used. Set 9.6 ms refresh time.
+*/
+ ldr r4, =0x01e0
+ str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+ /* Select mode register update mode. */
+ ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
+ EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
+ str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+ /* Program the mode register on the SDRAM by performing fake read */
+ ldr r4, [r2]
+
+ /* Select normal operating mode. */
+ ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
+ str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+ /* Return to the caller. */
+ mov pc, lr
+
+/*
+ * Test to see if the SDRAM has been configured in a usable mode.
+ *
+ * Input: r0 - Test address of SDRAM
+ * Output: r0 - 0 -- Test OK, -1 -- Failed
+ * Modifies: r0-r5
+ */
+ep93xx_sdram_test:
+ /* Load the test patterns to be written to SDRAM. */
+ ldr r1, =0xf00dface
+ ldr r2, =0xdeadbeef
+
