- Remove duplicate doc/README.p1010rdb
- Update for P1010RDB-PB board
P1010RDB-PB is a variation of previous P1010RDB-PA board.
Henceforth we support P1010RDB-PB board instead of P1010RDB-PA.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: add frequency combination support
v2: removed duplicate doc/README.p1010rdb
board/freescale/p1010rdb/README | 296 +++-
doc/README.p1010rdb | 199 ---
2 files changed, 138 insertions(+), 357 deletions(-)
delete mode 100644 doc/README.p1010rdb
diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README
index 7f18aaa..9473b14 100644
--- a/board/freescale/p1010rdb/README
+++ b/board/freescale/p1010rdb/README
@@ -1,58 +1,40 @@
Overview
=
-The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
+The P1010RDB is a Freescale Reference Design Board that hosts the P1010 SoC.
+P1010RDB-PB is a variation of previous P1010RDB-PA board.
The P1010 is a cost-effective, low-power, highly integrated host processor
-based on a Power Architecture e500v2 core (maximum core frequency 800/1000
MHz),
-that addresses the requirements of several routing, gateways, storage,
consumer,
+based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
+addresses the requirements of several routing, gateways, storage, consumer,
and industrial applications. Applications of interest include the main CPUs and
I/O processors in network attached storage (NAS), the voice over IP (VoIP)
router/gateway, and wireless LAN (WLAN) and industrial controllers.
-The P1010RDB board features are as follows:
+The P1010RDB-PB board features are as following:
Memory subsystem:
- - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- - 32 Mbyte NOR flash single-chip memory
- - 32 Mbyte NAND flash memory
- - 256 Kbit M24256 I2C EEPROM
- - 16 Mbyte SPI memory
+ - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ - 32M bytes NOR flash single-chip memory
+ - 2G bytes NAND flash memory
+ - 16M bytes SPI memory
+ - 256K bit M24256 I2C EEPROM
- I2C Board EEPROM 128x8 bit memory
- SD/MMC connector to interface with the SD memory card
Interfaces:
- - PCIe:
- - Lane0: x1 mini-PCIe slot
- - Lane1: x1 PCIe standard slot
- - SATA:
- - 1 internal SATA connector to 2.5” 160G SATA2 HDD
- - 1 eSATA connector to rear panel
- - 10/100/1000 BaseT Ethernet ports:
- - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
- - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
- - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
- - USB 2.0 port:
- - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
- - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
- - FlexCAN ports:
- - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
- interface;
- - DUART interface:
- - DUART interface: supports two UARTs up to 115200 bps for
- console display
- - RJ45 connectors are used for these 2 UART ports.
- - TDM
- - 2 FXS ports connected via an external SLIC to the TDM
interface.
- SLIC is controllled via SPI.
- - 1 FXO port connected via a relay to FXS for switchover to POTS
+ - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
+ - PCIe 2.0: two x1 mini-PCIe slots
+ - SATA 2.0: two SATA interfaces
+ - USB 2.0: one USB interface
+ - FlexCAN: two FlexCAN interfaces (revision 2.0B)
+ - UART: one USB-to-Serial interface
+ - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
+ 1 FXO port connected via a relay to FXS for switchover to POTS
+
Board connectors:
- Mini-ITX power supply connector
- JTAG/COP for debugging
-IEEE Std. 1588 signals for test and measurement
-Real-time clock on I2C bus
-POR
- - support critical POR setting changed via switch on board
-PCB
- - 6-layer routing (4-layer signals, 2-layer power and ground)
+POR: support critical POR setting changed via switch on board
+PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
Physical Memory Map on P1010RDB
===
@@ -77,132 +59,130 @@ Configure the serial port of the attached computer with
the following values:
-Flow Control: Hardware/None
-Settings of DIP-switch
-==
- SW4[1:4]= and SW6[4]=0 for boot from 16bit NOR flash
- SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
- SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
+P1010RDB-PB default DIP-switch settings
