Re: [U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7
Hi, I am picking up on this old thread. My main point is that I think the armv7 cache implementation is a good start and should go into U-Boot. Aneesh are you planning another patch set? Also see below: On Tue, May 17, 2011 at 2:58 AM, Aneesh V wrote: > Hi Wolfgang, > > On Tuesday 17 May 2011 03:01 PM, Wolfgang Denk wrote: >> Dear Aneesh V, >> >> In message<4dd23d3a.4010...@ti.com> you wrote: >>> How much of this is actually needed in the context of U-Boot? >>> >>> Please see above. As far as I know OMAP doesn't do DMA in U-Boot. >> >> Devices like USB oth Ethernet don't use DMA for data transfers? > > Ethernet support is not upstreamed yet. USB doesn't seem to be using > DMA on a quick check. There is DMA in the USB EHCI side and this also does d cache range invalidate / flush. Regards, Simon > > best regards, > Aneesh > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7
Hi Wolfgang, On Tuesday 17 May 2011 03:01 PM, Wolfgang Denk wrote: > Dear Aneesh V, > > In message<4dd23d3a.4010...@ti.com> you wrote: >> >>> How much of this is actually needed in the context of U-Boot? >> >> Please see above. As far as I know OMAP doesn't do DMA in U-Boot. > > Devices like USB oth Ethernet don't use DMA for data transfers? Ethernet support is not upstreamed yet. USB doesn't seem to be using DMA on a quick check. best regards, Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7
On Tuesday 17 May 2011 03:01 PM, Wolfgang Denk wrote: > Dear Aneesh V, > > In message<4dd23d3a.4010...@ti.com> you wrote: >> >>> How much of this is actually needed in the context of U-Boot? >> >> Please see above. As far as I know OMAP doesn't do DMA in U-Boot. > > Devices like USB oth Ethernet don't use DMA for data transfers? > >>> Please do not add dead code. I consider it misleading to have >>> functions which promise to perform something, and actually do nothing. >> >> These are empty only in the else part of an #ifdef. When cache support >> is compiled out these need to be empty. > > When cache support is compiled out there should be no callers to these > functions, so maybe they can disappear? No, there may be callers in drivers. It will be ugly to keep all the calls in various drivers under #ifdef, right? Is it not better to have some empty functions and not worrying about the calls in various places. best regards, Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7
Dear Aneesh V, In message <4dd23d3a.4010...@ti.com> you wrote: > > > How much of this is actually needed in the context of U-Boot? > > Please see above. As far as I know OMAP doesn't do DMA in U-Boot. Devices like USB oth Ethernet don't use DMA for data transfers? > > Please do not add dead code. I consider it misleading to have > > functions which promise to perform something, and actually do nothing. > > These are empty only in the else part of an #ifdef. When cache support > is compiled out these need to be empty. When cache support is compiled out there should be no callers to these functions, so maybe they can disappear? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de No journaling file system can recover your data if the disk dies. - Steve Rago in ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7
On Monday 16 May 2011 12:21 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305202276-27784-4-git-send-email-ane...@ti.com> you wrote:
>> - Add a framework for layered cache maintenance
>> - separate out SOC specific outer cache maintenance from
>>maintenance of caches known to CPU
>>
>> - Add generic ARMv7 cache maintenance operations that affect all
>>caches known to ARMv7 CPUs. For instance in Cortex-A8 these
>>opertions will affect both L1 and L2 caches. In Cortex-A9
>>these will affect only L1 cache
>>
>> - D-cache operations supported:
>> - Invalidate entire D-cache
Needed before enabling the caches.
>> - Invalidate D-cache range
Needed if you are doing DMA.
>> - Flush(clean& invalidate) entire D-cache
Needed before Linux before disabling the caches.
>> - Flush D-cache range
Needed in case of DMA out.
>
> How much of this is actually needed in the context of U-Boot?
Please see above. As far as I know OMAP doesn't do DMA in U-Boot.
>
> ...
>> +for (way = num_ways - 1; way>= 0 ; way--)
>> +for (set = num_sets - 1; set>= 0; set--) {
>> +setway = (level<< 1) | (set<< log2_line_len) |
>> + (way<< way_shift);
>> +/* Invalidate data/unified cache line by set/way */
>> +asm volatile (" mcr p15, 0, %0, c7, c6, 2"
>> +: : "r" (setway));
>> +}
>
> Braces needed for multiline for(). Please fix globally.
Ok.
>
> ...
>> +if (operation == ARMV7_DCACHE_INVAL_ALL)
>> +v7_inval_dcache_level_setway(level, num_sets, num_ways,
>> + way_shift, log2_line_len);
>> +else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL)
>> +v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
>> + way_shift, log2_line_len);
>
> Braces needed for multiline statements. Please fix globally.
>
>> +for (mva = start; mva< stop; mva = mva + line_len)
>> +/* DCCIMVAC - Clean& Invalidate data cache by MVA to PoC */
>> +asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
>
> And again etc. etc.
>
> ...
>> +void invalidate_dcache_all(void)
>> +{
>> +}
>> +
>> +void flush_dcache_all(void)
>> +{
>> +}
>> +
>> +void invalidate_dcache_range(unsigned long start, unsigned long stop)
>> +{
>> +}
>> +
>> +void flush_dcache_range(unsigned long start, unsigned long stop)
>> +{
>> +}
>> +
>> +void arm_init_before_mmu(void)
>> +{
>> +}
>> +
>> +void flush_cache(unsigned long start, unsigned long size)
>> +{
>> +}
>
> Please do not add dead code. I consider it misleading to have
> functions which promise to perform something, and actually do nothing.
These are empty only in the else part of an #ifdef. When cache support
is compiled out these need to be empty.
best regards,
Aneesh
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Re: [U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7
Dear Aneesh V,
In message <1305202276-27784-4-git-send-email-ane...@ti.com> you wrote:
> - Add a framework for layered cache maintenance
> - separate out SOC specific outer cache maintenance from
> maintenance of caches known to CPU
>
> - Add generic ARMv7 cache maintenance operations that affect all
> caches known to ARMv7 CPUs. For instance in Cortex-A8 these
> opertions will affect both L1 and L2 caches. In Cortex-A9
> these will affect only L1 cache
>
> - D-cache operations supported:
> - Invalidate entire D-cache
> - Invalidate D-cache range
> - Flush(clean & invalidate) entire D-cache
> - Flush D-cache range
How much of this is actually needed in the context of U-Boot?
...
> + for (way = num_ways - 1; way >= 0 ; way--)
> + for (set = num_sets - 1; set >= 0; set--) {
> + setway = (level << 1) | (set << log2_line_len) |
> + (way << way_shift);
> + /* Invalidate data/unified cache line by set/way */
> + asm volatile (" mcr p15, 0, %0, c7, c6, 2"
> + : : "r" (setway));
> + }
Braces needed for multiline for(). Please fix globally.
...
> + if (operation == ARMV7_DCACHE_INVAL_ALL)
> + v7_inval_dcache_level_setway(level, num_sets, num_ways,
> + way_shift, log2_line_len);
> + else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL)
> + v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
> +way_shift, log2_line_len);
Braces needed for multiline statements. Please fix globally.
> + for (mva = start; mva < stop; mva = mva + line_len)
> + /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
> + asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
And again etc. etc.
...
> +void invalidate_dcache_all(void)
> +{
> +}
> +
> +void flush_dcache_all(void)
> +{
> +}
> +
> +void invalidate_dcache_range(unsigned long start, unsigned long stop)
> +{
> +}
> +
> +void flush_dcache_range(unsigned long start, unsigned long stop)
> +{
> +}
> +
> +void arm_init_before_mmu(void)
> +{
> +}
> +
> +void flush_cache(unsigned long start, unsigned long size)
> +{
> +}
Please do not add dead code. I consider it misleading to have
functions which promise to perform something, and actually do nothing.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Gods don't like people not doing much work. People who aren't busy
all the time might start to _think_. - Terry Pratchett, _Small Gods_
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[U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU
- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache
- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache
- Add maintenance functions for TLB, branch predictor array etc.
- Enable -march=armv7-a so that armv7 assembly instructions can be
used
Signed-off-by: Aneesh V
---
V2:
* Blank line after local variable declarations - fixed globally
* Change from pointers to weakly linked functions for outer
cache operations
* Explicitly added a copy of flush_cache() under
#ifdefCONFIG_SYS_NO_DCACHE
* Change -march=armv7-a back to armv5
* Update documentation with cache related CONFIG options
---
README|5 +
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/armv7/cache_v7.c | 390 +
arch/arm/include/asm/armv7.h | 68 +++
include/common.h |5 +-
5 files changed, 468 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/cache_v7.c
create mode 100644 arch/arm/include/asm/armv7.h
diff --git a/README b/README
index 76b1500..c3b6bec 100644
--- a/README
+++ b/README
@@ -455,6 +455,11 @@ The following options need to be configured:
Note: If a "bootargs" environment is defined, it will overwride
the defaults discussed just above.
+- Cache Configuration:
+ CONFIG_SYS_NO_ICACHE - Do not enable instruction cache in U-Boot
+ CONFIG_SYS_NO_DCACHE - Do not enable data cache in U-Boot
+ CONFIG_SYS_NO_L2CACHE- Do not enable L2 cache in U-Boot
+
- Serial Ports:
CONFIG_PL010_SERIAL
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 8c0e915..299792a 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START := start.o
-COBJS := cpu.o
+COBJS := cpu.o cache_v7.o
COBJS += syslib.o
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
new file mode 100644
index 000..46d8e09
--- /dev/null
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -0,0 +1,390 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ * Aneesh V
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+#include
+#include
+
+#define ARMV7_DCACHE_INVAL_ALL 1
+#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
+#define ARMV7_DCACHE_INVAL_RANGE 3
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
+
+#ifndef CONFIG_SYS_NO_DCACHE
+/*
+ * Write the level and type you want to Cache Size Selection Register(CSSELR)
+ * to get size details from Current Cache Size ID Register(CCSIDR)
+ */
+static void set_csselr(u32 level, u32 type)
+{ u32 csselr = level << 1 | type;
+
+ /* Write to Cache Size Selection Register(CSSELR) */
+ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
+}
+
+static u32 get_ccsidr(void)
+{
+ u32 ccsidr;
+
+ /* Read current CP15 Cache Size ID Register */
+ asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
+ return ccsidr;
+}
+
+static u32 get_clidr(void)
+{
+ u32 clidr;
+
+ /* Read current CP15 Cache Level ID Register */
+ asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
+ return clidr;
+}
+
+static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
+u32 num_ways, u32 way_shift,
+u32 log2_line_len)
+{
+ int way, set, setway;
+
+ /*
+* For optimal assembly code:
+* a. count down
+* b. have bigger loop inside
+*/
+
