This patch adds support for RGMII protocol
NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Amrita Kumari
Signed-off-by: Ashish Kumar
---
v3:
No change
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 21 +
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 4
.../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 +
board/freescale/ls1088a/eth_ls1088aqds.c | 1 -
drivers/net/ldpaa_eth/ldpaa_wriop.c| 9
drivers/net/ldpaa_eth/ls1088a.c| 27 ++
include/fsl-mc/ldpaa_wriop.h | 2 ++
8 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9290268..2af7a76 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -57,6 +57,8 @@ config ARCH_LS1088A
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_EC1
+ select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
@@ -64,6 +66,7 @@ config ARCH_LS1088A
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
@@ -406,6 +409,18 @@ config RESV_RAM
be at the high end of physical memory. The reserve RAM may be
excluded from memory bank(s) passed to OS, or marked as reserved.
+config SYS_FSL_EC1
+ bool
+ help
+ Ethernet controller 1, this is connected to MAC3.
+ Provides DPAA2 capabilities
+
+config SYS_FSL_EC2
+ bool
+ help
+ Ethernet controller 2, this is connected to MAC4.
+ Provides DPAA2 capabilities
+
config SYS_FSL_ERRATUM_A008336
bool
@@ -430,6 +445,12 @@ config SYS_FSL_ERRATUM_A009660
config SYS_FSL_ERRATUM_A009929
bool
+
+config SYS_FSL_HAS_RGMII
+ bool
+ depends on SYS_FSL_EC1 || SYS_FSL_EC2
+
+
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ec58065..3c9a5ed 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -517,6 +517,10 @@ int arch_early_init_r(void)
printf("Did not wake secondary cores\n");
}
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+ fsl_rgmii_init();
+#endif
+
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index a2c7578..12fd6b8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -159,6 +159,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
int serdes_get_number(int serdes, int cfg);
+void fsl_rgmii_init(void);
#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 99a7413..ffc5fa2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -247,6 +247,12 @@ struct ccsr_gur {
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_EC1_REGSR 26
+#define FSL_CHASSIS3_EC2_REGSR 26
+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x0007
+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT0
+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x0038
+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT3
#defineFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0x
#defineFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
#defineFSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c
b/board/freescale/ls1088a/eth_ls1088aqds.c
index a912ff7..a973457 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -597,7 +597,6 @@ int board_eth_init(bd_t *bis)
/* Register the real MDIO1 bus */
fm_memac_mdio_init(bis, memac_mdio0_info);
-
/* Register the muxing front-ends to the MDIO buses */
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
ls1088a
