Re: [U-Boot] [PATCH v3 1/2] wandboard: Add support for the latest revd1 revision

[Stefano Babic]

Hi Fabio,

On 27/09/2017 19:27, Fabio Estevam wrote:
> Latest wandboard hardware revision is revd1, which brings the following
> new features:
> 
> - PFUZE100 PMIC
> - AR8035 Ethernet PHY
> - Upgrade Wifi/BT chip to BCM4339/BCM43430.
> 

This patch cannot be applied anymore - as you will be preparing 2/2,
could you also rebase this on current u-boot-imx ? Thanks !

Best regards,
Stefano

> The detection mechanism is to probe the PMIC and when it is
> found, then the revision of the board is revd1.
> 
> As the detection is done via PMIC, we need to print the board version
> at a later stage via CONFIG_DISPLAY_BOARDINFO_LATE and also need
> to disable CONFIG_DISPLAY_BOARDINFO, which is done much earlier.
> 
> Make the necessary adjustments for the AR8035 PHY to work on revd1.
> 
> Based on Richard Hu's work from Technexion's U-Boot tree.
> 
> Signed-off-by: Fabio Estevam 
> ---
> Changes since v2:
> - Also turn on ldb_di0 clock. Able to boot the kernel now.
> 
>  board/wandboard/wandboard.c | 110 
> +---
>  configs/wandboard_defconfig |   1 +
>  include/configs/wandboard.h |  11 +
>  3 files changed, 115 insertions(+), 7 deletions(-)
> 
> diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
> index adfcf48..14dd378 100644
> --- a/board/wandboard/wandboard.c
> +++ b/board/wandboard/wandboard.c
> @@ -30,6 +30,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -51,8 +53,11 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define USDHC1_CD_GPIO   IMX_GPIO_NR(1, 2)
>  #define USDHC3_CD_GPIO   IMX_GPIO_NR(3, 9)
>  #define ETH_PHY_RESETIMX_GPIO_NR(3, 29)
> +#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
>  #define REV_DETECTIONIMX_GPIO_NR(2, 28)
>  
> +static bool with_pmic;
> +
>  int dram_init(void)
>  {
>   gd->ram_size = imx_ddr_size();
> @@ -107,6 +112,11 @@ static iomux_v3_cfg_t const enet_pads[] = {
>   IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29| MUX_PAD_CTRL(NO_PAD_CTRL)),
>  };
>  
> +static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
> + /* AR8035 POWER */
> + IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13| MUX_PAD_CTRL(NO_PAD_CTRL)),
> +};
> +
>  static iomux_v3_cfg_t const rev_detection_pad[] = {
>   IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
>  };
> @@ -120,6 +130,14 @@ static void setup_iomux_enet(void)
>  {
>   SETUP_IOMUX_PADS(enet_pads);
>  
> + if (with_pmic) {
> + SETUP_IOMUX_PADS(enet_ar8035_power_pads);
> + /* enable AR8035 POWER */
> + gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
> + }
> + /* wait until 3.3V of PHY and clock become stable */
> + mdelay(10);
> +
>   /* Reset AR8031 PHY */
>   gpio_direction_output(ETH_PHY_RESET, 0);
>   mdelay(10);
> @@ -192,6 +210,7 @@ int board_mmc_init(bd_t *bis)
>  static int ar8031_phy_fixup(struct phy_device *phydev)
>  {
>   unsigned short val;
> + int mask;
>  
>   /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
>   phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
> @@ -199,7 +218,12 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
>   phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
>  
>   val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> - val &= 0xffe3;
> + if (with_pmic)
> + mask = 0xffe7;  /* AR8035 */
> + else
> + mask = 0xffe3;  /* AR8031 */
> +
> + val &= mask;
>   val |= 0x18;
>   phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
>  
> @@ -257,6 +281,40 @@ struct i2c_pads_info mx6dl_i2c2_pad_info = {
>   }
>  };
>  
> +struct i2c_pads_info mx6q_i2c3_pad_info = {
> + .scl = {
> + .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gp = IMX_GPIO_NR(1, 5)
> + },
> + .sda = {
> + .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gp = IMX_GPIO_NR(7, 11)
> + }
> +};
> +
> +struct i2c_pads_info mx6dl_i2c3_pad_info = {
> + .scl = {
> + .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gp = IMX_GPIO_NR(1, 5)
> + },
> + .sda = {
> + .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gp = IMX_GPIO_NR(7, 11)
> + }
> +};
> +
>  static 

[U-Boot] [PATCH v3 1/2] wandboard: Add support for the latest revd1 revision

[Fabio Estevam]

Latest wandboard hardware revision is revd1, which brings the following
new features:

- PFUZE100 PMIC
- AR8035 Ethernet PHY
- Upgrade Wifi/BT chip to BCM4339/BCM43430.

The detection mechanism is to probe the PMIC and when it is
found, then the revision of the board is revd1.

As the detection is done via PMIC, we need to print the board version
at a later stage via CONFIG_DISPLAY_BOARDINFO_LATE and also need
to disable CONFIG_DISPLAY_BOARDINFO, which is done much earlier.

Make the necessary adjustments for the AR8035 PHY to work on revd1.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam 
---
Changes since v2:
- Also turn on ldb_di0 clock. Able to boot the kernel now.

 board/wandboard/wandboard.c | 110 +---
 configs/wandboard_defconfig |   1 +
 include/configs/wandboard.h |  11 +
 3 files changed, 115 insertions(+), 7 deletions(-)

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index adfcf48..14dd378 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -30,6 +30,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,8 +53,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
 #define ETH_PHY_RESET  IMX_GPIO_NR(3, 29)
+#define ETH_PHY_AR8035_POWER   IMX_GPIO_NR(7, 13)
 #define REV_DETECTION  IMX_GPIO_NR(2, 28)
 
+static bool with_pmic;
+
 int dram_init(void)
 {
gd->ram_size = imx_ddr_size();
@@ -107,6 +112,11 @@ static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29| MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
+static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
+   /* AR8035 POWER */
+   IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const rev_detection_pad[] = {
IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
@@ -120,6 +130,14 @@ static void setup_iomux_enet(void)
 {
SETUP_IOMUX_PADS(enet_pads);
 
+   if (with_pmic) {
+   SETUP_IOMUX_PADS(enet_ar8035_power_pads);
+   /* enable AR8035 POWER */
+   gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
+   }
+   /* wait until 3.3V of PHY and clock become stable */
+   mdelay(10);
+
/* Reset AR8031 PHY */
gpio_direction_output(ETH_PHY_RESET, 0);
mdelay(10);
@@ -192,6 +210,7 @@ int board_mmc_init(bd_t *bis)
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
unsigned short val;
+   int mask;
 
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
@@ -199,7 +218,12 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-   val &= 0xffe3;
+   if (with_pmic)
+   mask = 0xffe7;  /* AR8035 */
+   else
+   mask = 0xffe3;  /* AR8031 */
+
+   val &= mask;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 
@@ -257,6 +281,40 @@ struct i2c_pads_info mx6dl_i2c2_pad_info = {
}
 };
 
+struct i2c_pads_info mx6q_i2c3_pad_info = {
+   .scl = {
+   .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gp = IMX_GPIO_NR(1, 5)
+   },
+   .sda = {
+   .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gp = IMX_GPIO_NR(7, 11)
+   }
+};
+
+struct i2c_pads_info mx6dl_i2c3_pad_info = {
+   .scl = {
+   .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gp = IMX_GPIO_NR(1, 5)
+   },
+   .sda = {
+   .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
+   | MUX_PAD_CTRL(I2C_PAD_CTRL),
+   .gp = IMX_GPIO_NR(7, 11)
+   }
+};
+
 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
@@ -388,6 +446,31 @@ int board_early_init_f(void)
return 0;
 }
 
+#define PMIC_I2C_BUS   2
+
+int power_init_board(void)
+{
+   struct pmic *p;
+   u32 reg;
+
+   /* configure PFUZE100 PMIC */
+