Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.
Signed-off-by: Sumit Garg
Tested-by: Vinitha Pillai
---
Changes in v3:
Rebasing of the patch on top commit.
This patch supersedes https://patchwork.ozlabs.org/patch/756260/
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 +++
arch/arm/include/asm/fsl_secure_boot.h| 54 +--
2 files changed, 28 insertions(+), 38 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5825f9b..b7549a0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -194,12 +194,12 @@ config SYS_LS_PPA_FW_ADDR
config SYS_LS_PPA_ESBC_ADDR
hex "hdr address of PPA firmware loading from"
depends on FSL_LS_PPA && CHAIN_OF_TRUST
- default 0x600c if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
- default 0x4074 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
- default 0x4048 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
- default 0x580c4 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
- default 0x70 if SYS_LS_PPA_FW_IN_MMC
- default 0x70 if SYS_LS_PPA_FW_IN_NAND
+ default 0x6068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+ default 0x4068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+ default 0x4068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
+ default 0x58068 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+ default 0x68 if SYS_LS_PPA_FW_IN_MMC
+ default 0x68 if SYS_LS_PPA_FW_IN_NAND
help
If the PPA header firmware locate at XIP flash, such as NOR or
QSPI flash, this address is a directly memory-mapped.
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index b0b3b93..63845a2 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -1,5 +1,6 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -71,55 +72,44 @@
* DDR memory map
*/
#ifdef CONFIG_FSL_LSCH3
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d0
-#define CONFIG_BS_ADDR_DEVICE 0x580e0
-#define CONFIG_BS_HDR_ADDR_RAM 0xa0d0
-#define CONFIG_BS_ADDR_RAM 0xa0e0
-#define CONFIG_BS_HDR_SIZE 0x2000
+#define CONFIG_BS_ADDR_DEVICE 0x58060
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x58064
#define CONFIG_BS_SIZE 0x1000
+#define CONFIG_BS_HDR_SIZE 0x4000
+#define CONFIG_BS_ADDR_RAM 0xa060
+#define CONFIG_BS_HDR_ADDR_RAM 0xa064
#else
#ifdef CONFIG_SD_BOOT
/* For SD boot address and size are assigned in terms of sector
* offset and no. of sectors respectively.
*/
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x0920
-#else
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x0900
-#endif
-#define CONFIG_BS_ADDR_DEVICE 0x0940
-#define CONFIG_BS_HDR_SIZE 0x0010
+#define CONFIG_BS_ADDR_DEVICE 0x3000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x3200
#define CONFIG_BS_SIZE 0x0008
+#define CONFIG_BS_HDR_SIZE 0x0010
#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x0080
-#define CONFIG_BS_ADDR_DEVICE 0x00802000
-#define CONFIG_BS_HDR_SIZE 0x2000
-#define CONFIG_BS_SIZE 0x1000
-#elif defined(CONFIG_QSPI_BOOT)
-#ifdef CONFIG_ARCH_LS1046A
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x4078
-#define CONFIG_BS_ADDR_DEVICE 0x4080
-#elif defined(CONFIG_ARCH_LS1012A)
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c
-#define CONFIG_BS_ADDR_DEVICE 0x4006
-#else
-#error "Platform not supported"
-#endif
+#define CONFIG_BS_ADDR_DEVICE 0x0060
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x0064
+#define CONFIG_BS_SIZE 0x1000
#define CONFIG_BS_HDR_SIZE 0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BS_ADDR_DEVICE 0x4060
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x4064
#define CONFIG_BS_SIZE 0x1000
-#else /* Default NOR Boot */
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a
-#define CONFIG_BS_ADDR_DEVICE 0x6006
#define CONFIG_BS_HDR_SIZE 0x2000
+#else /* Default NOR Boot */
+#define CONFIG_BS_ADDR_DEVICE 0x6060
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x6064
#define CONFIG_BS_SIZE 0x1000
+#define CONFIG_BS_HDR_SIZE 0x2000
#endif
-#define CONFIG_BS_HDR_ADDR_RAM 0x8100
-#define CONFIG_BS_ADDR_RAM 0x8102
+#define CONFIG_BS_ADDR_RAM 0x8100
