subject:"\[U\-Boot\] \[PATCH v3 1\/9\] sunxi\: clk\: add MMC gates\/resets"

Re: [U-Boot] [PATCH v3 1/9] sunxi: clk: add MMC gates/resets

2019-01-22 Thread André Przywara

On 21/01/2019 10:31, Jagan Teki wrote:
> From: Andre Przywara 
> 
> Add the MMC clock gates and reset bits for all the Allwinner SoCs.
> This allows them to be used by the MMC driver.
> 
> We don't advertise the mod clock yet, as this is still handled by the
> MMC driver.
> 
> Signed-off-by: Andre Przywara 
> [jagan: add V3S gates/resets, fix CLK_AHB1_MMC3 bit]

Thanks for adding the V3S (looks correct to me), but the CLK_AHB1_MMC3
for the A31 smells like a Linux bug copied: According to the manual this
is bit 11, and Linux seems to be off-by-one here (check the next bit!).
Sent a fix for Linux.
Please set this back to bit 11 here.

Cheers,
Andre.

> Signed-off-by: Jagan Teki 
> ---
>  drivers/clk/sunxi/clk_a10.c  | 4 
>  drivers/clk/sunxi/clk_a10s.c | 3 +++
>  drivers/clk/sunxi/clk_a23.c  | 6 ++
>  drivers/clk/sunxi/clk_a31.c  | 8 
>  drivers/clk/sunxi/clk_a64.c  | 6 ++
>  drivers/clk/sunxi/clk_a83t.c | 6 ++
>  drivers/clk/sunxi/clk_h3.c   | 6 ++
>  drivers/clk/sunxi/clk_h6.c   | 6 ++
>  drivers/clk/sunxi/clk_r40.c  | 8 
>  drivers/clk/sunxi/clk_v3s.c  | 6 ++
>  10 files changed, 59 insertions(+)
> 
> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
> index b00f51af8b..2aa41efe17 100644
> --- a/drivers/clk/sunxi/clk_a10.c
> +++ b/drivers/clk/sunxi/clk_a10.c
> @@ -18,6 +18,10 @@ static struct ccu_clk_gate a10_gates[] = {
>   [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)),
>   [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)),
>   [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),
> + [CLK_AHB_MMC0]  = GATE(0x060, BIT(8)),
> + [CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
> + [CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
> + [CLK_AHB_MMC3]  = GATE(0x060, BIT(11)),
>  
>   [CLK_APB1_UART0]= GATE(0x06c, BIT(16)),
>   [CLK_APB1_UART1]= GATE(0x06c, BIT(17)),
> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
> index aa904ce067..87b74e52dc 100644
> --- a/drivers/clk/sunxi/clk_a10s.c
> +++ b/drivers/clk/sunxi/clk_a10s.c
> @@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = {
>   [CLK_AHB_OTG]   = GATE(0x060, BIT(0)),
>   [CLK_AHB_EHCI]  = GATE(0x060, BIT(1)),
>   [CLK_AHB_OHCI]  = GATE(0x060, BIT(2)),
> + [CLK_AHB_MMC0]  = GATE(0x060, BIT(8)),
> + [CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
> + [CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
>  
>   [CLK_APB1_UART0]= GATE(0x06c, BIT(16)),
>   [CLK_APB1_UART1]= GATE(0x06c, BIT(17)),
> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
> index 854259bf81..1ef2359286 100644
> --- a/drivers/clk/sunxi/clk_a23.c
> +++ b/drivers/clk/sunxi/clk_a23.c
> @@ -13,6 +13,9 @@
>  #include 
>  
>  static struct ccu_clk_gate a23_gates[] = {
> + [CLK_BUS_MMC0]  = GATE(0x060, BIT(8)),
> + [CLK_BUS_MMC1]  = GATE(0x060, BIT(9)),
> + [CLK_BUS_MMC2]  = GATE(0x060, BIT(10)),
>   [CLK_BUS_OTG]   = GATE(0x060, BIT(24)),
>   [CLK_BUS_EHCI]  = GATE(0x060, BIT(26)),
>   [CLK_BUS_OHCI]  = GATE(0x060, BIT(29)),
> @@ -35,6 +38,9 @@ static struct ccu_reset a23_resets[] = {
>   [RST_USB_PHY1]  = RESET(0x0cc, BIT(1)),
>   [RST_USB_HSIC]  = RESET(0x0cc, BIT(2)),
>  
> + [RST_BUS_MMC0]  = RESET(0x2c0, BIT(8)),
> + [RST_BUS_MMC1]  = RESET(0x2c0, BIT(9)),
> + [RST_BUS_MMC2]  = RESET(0x2c0, BIT(10)),
>   [RST_BUS_OTG]   = RESET(0x2c0, BIT(24)),
>   [RST_BUS_EHCI]  = RESET(0x2c0, BIT(26)),
>   [RST_BUS_OHCI]  = RESET(0x2c0, BIT(29)),
> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
> index a38d76cb7c..fa81f9a710 100644
> --- a/drivers/clk/sunxi/clk_a31.c
> +++ b/drivers/clk/sunxi/clk_a31.c
> @@ -13,6 +13,10 @@
>  #include 
>  
>  static struct ccu_clk_gate a31_gates[] = {
> + [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
> + [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
> + [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
> + [CLK_AHB1_MMC3] = GATE(0x060, BIT(12)),
>   [CLK_AHB1_OTG]  = GATE(0x060, BIT(24)),
>   [CLK_AHB1_EHCI0]= GATE(0x060, BIT(26)),
>   [CLK_AHB1_EHCI1]= GATE(0x060, BIT(27)),
> @@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = {
>   [RST_USB_PHY1]  = RESET(0x0cc, BIT(1)),
>   [RST_USB_PHY2]  = RESET(0x0cc, BIT(2)),
>  
> + [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
> + [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
> + [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
> + [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
>   [RST_AHB1_OTG]  = RESET(0x2c0, BIT(24)),
>   [RST_AHB1_EHCI0]= RESET(0x2c0, BIT(26)),
>   [RST_AHB1_EHCI1]= RESET(0x2c0, BIT(27)),
> diff --git a/drivers/clk/sunxi/clk_a64

[U-Boot] [PATCH v3 1/9] sunxi: clk: add MMC gates/resets

2019-01-21 Thread Jagan Teki

From: Andre Przywara 

Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.

We don't advertise the mod clock yet, as this is still handled by the
MMC driver.

Signed-off-by: Andre Przywara 
[jagan: add V3S gates/resets, fix CLK_AHB1_MMC3 bit]
Signed-off-by: Jagan Teki 
---
 drivers/clk/sunxi/clk_a10.c  | 4 
 drivers/clk/sunxi/clk_a10s.c | 3 +++
 drivers/clk/sunxi/clk_a23.c  | 6 ++
 drivers/clk/sunxi/clk_a31.c  | 8 
 drivers/clk/sunxi/clk_a64.c  | 6 ++
 drivers/clk/sunxi/clk_a83t.c | 6 ++
 drivers/clk/sunxi/clk_h3.c   | 6 ++
 drivers/clk/sunxi/clk_h6.c   | 6 ++
 drivers/clk/sunxi/clk_r40.c  | 8 
 drivers/clk/sunxi/clk_v3s.c  | 6 ++
 10 files changed, 59 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index b00f51af8b..2aa41efe17 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -18,6 +18,10 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_AHB_OHCI0] = GATE(0x060, BIT(2)),
[CLK_AHB_EHCI1] = GATE(0x060, BIT(3)),
[CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),
+   [CLK_AHB_MMC0]  = GATE(0x060, BIT(8)),
+   [CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
+   [CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
+   [CLK_AHB_MMC3]  = GATE(0x060, BIT(11)),
 
[CLK_APB1_UART0]= GATE(0x06c, BIT(16)),
[CLK_APB1_UART1]= GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index aa904ce067..87b74e52dc 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_OTG]   = GATE(0x060, BIT(0)),
[CLK_AHB_EHCI]  = GATE(0x060, BIT(1)),
[CLK_AHB_OHCI]  = GATE(0x060, BIT(2)),
+   [CLK_AHB_MMC0]  = GATE(0x060, BIT(8)),
+   [CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
+   [CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
 
[CLK_APB1_UART0]= GATE(0x06c, BIT(16)),
[CLK_APB1_UART1]= GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 854259bf81..1ef2359286 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -13,6 +13,9 @@
 #include 
 
 static struct ccu_clk_gate a23_gates[] = {
+   [CLK_BUS_MMC0]  = GATE(0x060, BIT(8)),
+   [CLK_BUS_MMC1]  = GATE(0x060, BIT(9)),
+   [CLK_BUS_MMC2]  = GATE(0x060, BIT(10)),
[CLK_BUS_OTG]   = GATE(0x060, BIT(24)),
[CLK_BUS_EHCI]  = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI]  = GATE(0x060, BIT(29)),
@@ -35,6 +38,9 @@ static struct ccu_reset a23_resets[] = {
[RST_USB_PHY1]  = RESET(0x0cc, BIT(1)),
[RST_USB_HSIC]  = RESET(0x0cc, BIT(2)),
 
+   [RST_BUS_MMC0]  = RESET(0x2c0, BIT(8)),
+   [RST_BUS_MMC1]  = RESET(0x2c0, BIT(9)),
+   [RST_BUS_MMC2]  = RESET(0x2c0, BIT(10)),
[RST_BUS_OTG]   = RESET(0x2c0, BIT(24)),
[RST_BUS_EHCI]  = RESET(0x2c0, BIT(26)),
[RST_BUS_OHCI]  = RESET(0x2c0, BIT(29)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index a38d76cb7c..fa81f9a710 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -13,6 +13,10 @@
 #include 
 
 static struct ccu_clk_gate a31_gates[] = {
+   [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
+   [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
+   [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
+   [CLK_AHB1_MMC3] = GATE(0x060, BIT(12)),
[CLK_AHB1_OTG]  = GATE(0x060, BIT(24)),
[CLK_AHB1_EHCI0]= GATE(0x060, BIT(26)),
[CLK_AHB1_EHCI1]= GATE(0x060, BIT(27)),
@@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = {
[RST_USB_PHY1]  = RESET(0x0cc, BIT(1)),
[RST_USB_PHY2]  = RESET(0x0cc, BIT(2)),
 
+   [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
+   [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
+   [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
+   [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
[RST_AHB1_OTG]  = RESET(0x2c0, BIT(24)),
[RST_AHB1_EHCI0]= RESET(0x2c0, BIT(26)),
[RST_AHB1_EHCI1]= RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index a2ba6eefc5..910275fbce 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -13,6 +13,9 @@
 #include 
 
 static const struct ccu_clk_gate a64_gates[] = {
+   [CLK_BUS_MMC0]  = GATE(0x060, BIT(8)),
+   [CLK_BUS_MMC1]  = GATE(0x060, BIT(9)),
+   [CLK_BUS_MMC2]  = GATE(0x060, BIT(10)),
[CLK_BUS_OTG]   = GATE(0x060, BIT(23)),

Re: [U-Boot] [PATCH v3 1/9] sunxi: clk: add MMC gates/resets

[U-Boot] [PATCH v3 1/9] sunxi: clk: add MMC gates/resets

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