[U-Boot] [PATCH v3 2/2] arm64: zynqmp: add tool to convert PMU config object .c to binary

2019-04-15 Thread Luca Ceresoli 
The recently-added ZYNQMP_LOAD_PM_CFG_OBJ_FILE option allows SPL to load a
PMUFW configuration object from a binary blob. However the configuration
object is produced by Xilinx proprietary tools as a C source file and no
tool exists to easily convert it to a binary blob in an embedded Linux
build system for U-Boot to use.

Add a simple Python script to do the conversion.

It is definitely not a complete C language parser, but it is enough to
parse the known patterns generated by Xilinx tools, including:

 - defines
 - literal integers, optionally with a 'U' suffix
 - bitwise OR between them

Signed-off-by: Luca Ceresoli 
---
 arch/arm/mach-zynqmp/pm_cfg_obj_convert.py | 302 +
 1 file changed, 302 insertions(+)
 create mode 100755 arch/arm/mach-zynqmp/pm_cfg_obj_convert.py

diff --git a/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py 
b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
new file mode 100755
index ..5aea15860319
--- /dev/null
+++ b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
@@ -0,0 +1,302 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019 Luca Ceresoli 
+
+import sys
+import re
+import struct
+import logging
+import argparse
+
+parser = argparse.ArgumentParser(
+description='Convert a PMU configuration object from C source to a binary 
blob.',
+allow_abbrev=False)
+parser.add_argument('-D', '--debug', action="store_true")
+parser.add_argument(
+"in_file", metavar='INPUT_FILE',
+help='PMU configuration object (C source as produced by Xilinx XSDK)')
+parser.add_argument(
+"out_file", metavar='OUTPUT_FILE',
+help='PMU configuration object binary blob')
+args = parser.parse_args()
+
+logging.basicConfig(format='%(levelname)s:%(message)s',
+level=(logging.DEBUG if args.debug else logging.WARNING))
+
+pm_define = {
+'PM_CAP_ACCESS'   : 0x1,
+'PM_CAP_CONTEXT'  : 0x2,
+'PM_CAP_WAKEUP'   : 0x4,
+
+'NODE_UNKNOWN':  0,
+'NODE_APU':  1,
+'NODE_APU_0'  :  2,
+'NODE_APU_1'  :  3,
+'NODE_APU_2'  :  4,
+'NODE_APU_3'  :  5,
+'NODE_RPU':  6,
+'NODE_RPU_0'  :  7,
+'NODE_RPU_1'  :  8,
+'NODE_PLD':  9,
+'NODE_FPD': 10,
+'NODE_OCM_BANK_0' : 11,
+'NODE_OCM_BANK_1' : 12,
+'NODE_OCM_BANK_2' : 13,
+'NODE_OCM_BANK_3' : 14,
+'NODE_TCM_0_A': 15,
+'NODE_TCM_0_B': 16,
+'NODE_TCM_1_A': 17,
+'NODE_TCM_1_B': 18,
+'NODE_L2' : 19,
+'NODE_GPU_PP_0'   : 20,
+'NODE_GPU_PP_1'   : 21,
+'NODE_USB_0'  : 22,
+'NODE_USB_1'  : 23,
+'NODE_TTC_0'  : 24,
+'NODE_TTC_1'  : 25,
+'NODE_TTC_2'  : 26,
+'NODE_TTC_3'  : 27,
+'NODE_SATA'   : 28,
+'NODE_ETH_0'  : 29,
+'NODE_ETH_1'  : 30,
+'NODE_ETH_2'  : 31,
+'NODE_ETH_3'  : 32,
+'NODE_UART_0' : 33,
+'NODE_UART_1' : 34,
+'NODE_SPI_0'  : 35,
+'NODE_SPI_1'  : 36,
+'NODE_I2C_0'  : 37,
+'NODE_I2C_1'  : 38,
+'NODE_SD_0'   : 39,
+'NODE_SD_1'   : 40,
+'NODE_DP' : 41,
+'NODE_GDMA'   : 42,
+'NODE_ADMA'   : 43,
+'NODE_NAND'   : 44,
+'NODE_QSPI'   : 45,
+'NODE_GPIO'   : 46,
+'NODE_CAN_0'  : 47,
+'NODE_CAN_1'  : 48,
+'NODE_EXTERN' : 49,
+'NODE_APLL'   : 50,
+'NODE_VPLL'   : 51,
+'NODE_DPLL'   : 52,
+'NODE_RPLL'   : 53,
+'NODE_IOPLL'  : 54,
+'NODE_DDR': 55,
+'NODE_IPI_APU': 56,
+'NODE_IPI_RPU_0'  : 57,
+'NODE_GPU': 58,
+'NODE_PCIE'   : 59,
+'NODE_PCAP'   : 60,
+'NODE_RTC': 61,
+'NODE_LPD': 62,
+'NODE_VCU': 63,
+'NODE_IPI_RPU_1'  : 64,
+'NODE_IPI_PL_0'   : 65,
+'NODE_IPI_PL_1'   : 66,
+'NODE_IPI_PL_2'   : 67,
+'NODE_IPI_PL_3'   : 68,
+'NODE_PL' : 69,
+'NODE_ID_MA'  : 70,
+
+'XILPM_RESET_PCIE_CFG' : 1000,
+'XILPM_RESET_PCIE_BRIDGE'  : 1001,
+'XILPM_RESET_PCIE_CTRL': 1002,
+'XILPM_RESET_DP'   : 1003,
+'XILPM_RESET_SWDT_CRF' : 1004,
+'XILPM_RESET_AFI_FM5'  : 1005,
+'XILPM_RESET_AFI_FM4'  : 1006,
+'XILPM_RESET_AFI_FM3'  : 1007,
+'XILPM_RESET_AFI_FM2'  : 1008,
+'XILPM_RESET_AFI_FM1'  : 1009,
+'XILPM_RESET_AFI_FM0'  : 1010,
+'XILPM_RESET_GDMA' : 1011,
+'XILPM_RESET_GPU_PP1'  : 1012,
+'XILPM_RESET_GPU_PP0'  : 1013,
+'XILPM_RESET_GPU'  : 1014,
+'XILPM_RESET_GT'   : 1015,
+'XILPM_RESET_SATA' : 1016,
+'XILPM_RESET_ACPU3_PWRON'  : 1017,
+'XILPM_RESET_ACPU2_PWRON'  : 1018,
+'XILPM_RESET_ACPU1_PWRON'  : 1019,
+'XILPM_RESET_ACPU0_PWRON'  : 1020,
+'XILPM_RESET_APU_L2'   : 1021,
+'XILPM_RESET_ACPU3'

Re: [U-Boot] [PATCH v3 2/2] arm64: zynqmp: add tool to convert PMU config object .c to binary

2019-05-03 Thread Michal Simek 
Hi,

On 15. 04. 19 9:47, Luca Ceresoli wrote:
> The recently-added ZYNQMP_LOAD_PM_CFG_OBJ_FILE option allows SPL to load a
> PMUFW configuration object from a binary blob. However the configuration
> object is produced by Xilinx proprietary tools as a C source file and no
> tool exists to easily convert it to a binary blob in an embedded Linux
> build system for U-Boot to use.
> 
> Add a simple Python script to do the conversion.
> 
> It is definitely not a complete C language parser, but it is enough to
> parse the known patterns generated by Xilinx tools, including:
> 
>  - defines
>  - literal integers, optionally with a 'U' suffix
>  - bitwise OR between them
> 
> Signed-off-by: Luca Ceresoli 
> ---
>  arch/arm/mach-zynqmp/pm_cfg_obj_convert.py | 302 +
>  1 file changed, 302 insertions(+)
>  create mode 100755 arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> 
> diff --git a/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py 
> b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> new file mode 100755
> index ..5aea15860319
> --- /dev/null
> +++ b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> @@ -0,0 +1,302 @@
> +#!/usr/bin/env python3
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (C) 2019 Luca Ceresoli 
> +
> +import sys
> +import re
> +import struct
> +import logging
> +import argparse
> +
> +parser = argparse.ArgumentParser(
> +description='Convert a PMU configuration object from C source to a 
> binary blob.',
> +allow_abbrev=False)
> +parser.add_argument('-D', '--debug', action="store_true")
> +parser.add_argument(
> +"in_file", metavar='INPUT_FILE',
> +help='PMU configuration object (C source as produced by Xilinx XSDK)')
> +parser.add_argument(
> +"out_file", metavar='OUTPUT_FILE',
> +help='PMU configuration object binary blob')
> +args = parser.parse_args()
> +
> +logging.basicConfig(format='%(levelname)s:%(message)s',
> +level=(logging.DEBUG if args.debug else logging.WARNING))
> +
> +pm_define = {
> +'PM_CAP_ACCESS'   : 0x1,
> +'PM_CAP_CONTEXT'  : 0x2,
> +'PM_CAP_WAKEUP'   : 0x4,
> +
> +'NODE_UNKNOWN':  0,
> +'NODE_APU':  1,
> +'NODE_APU_0'  :  2,
> +'NODE_APU_1'  :  3,
> +'NODE_APU_2'  :  4,
> +'NODE_APU_3'  :  5,
> +'NODE_RPU':  6,
> +'NODE_RPU_0'  :  7,
> +'NODE_RPU_1'  :  8,
> +'NODE_PLD':  9,
> +'NODE_FPD': 10,
> +'NODE_OCM_BANK_0' : 11,
> +'NODE_OCM_BANK_1' : 12,
> +'NODE_OCM_BANK_2' : 13,
> +'NODE_OCM_BANK_3' : 14,
> +'NODE_TCM_0_A': 15,
> +'NODE_TCM_0_B': 16,
> +'NODE_TCM_1_A': 17,
> +'NODE_TCM_1_B': 18,
> +'NODE_L2' : 19,
> +'NODE_GPU_PP_0'   : 20,
> +'NODE_GPU_PP_1'   : 21,
> +'NODE_USB_0'  : 22,
> +'NODE_USB_1'  : 23,
> +'NODE_TTC_0'  : 24,
> +'NODE_TTC_1'  : 25,
> +'NODE_TTC_2'  : 26,
> +'NODE_TTC_3'  : 27,
> +'NODE_SATA'   : 28,
> +'NODE_ETH_0'  : 29,
> +'NODE_ETH_1'  : 30,
> +'NODE_ETH_2'  : 31,
> +'NODE_ETH_3'  : 32,
> +'NODE_UART_0' : 33,
> +'NODE_UART_1' : 34,
> +'NODE_SPI_0'  : 35,
> +'NODE_SPI_1'  : 36,
> +'NODE_I2C_0'  : 37,
> +'NODE_I2C_1'  : 38,
> +'NODE_SD_0'   : 39,
> +'NODE_SD_1'   : 40,
> +'NODE_DP' : 41,
> +'NODE_GDMA'   : 42,
> +'NODE_ADMA'   : 43,
> +'NODE_NAND'   : 44,
> +'NODE_QSPI'   : 45,
> +'NODE_GPIO'   : 46,
> +'NODE_CAN_0'  : 47,
> +'NODE_CAN_1'  : 48,
> +'NODE_EXTERN' : 49,
> +'NODE_APLL'   : 50,
> +'NODE_VPLL'   : 51,
> +'NODE_DPLL'   : 52,
> +'NODE_RPLL'   : 53,
> +'NODE_IOPLL'  : 54,
> +'NODE_DDR': 55,
> +'NODE_IPI_APU': 56,
> +'NODE_IPI_RPU_0'  : 57,
> +'NODE_GPU': 58,
> +'NODE_PCIE'   : 59,
> +'NODE_PCAP'   : 60,
> +'NODE_RTC': 61,
> +'NODE_LPD': 62,
> +'NODE_VCU': 63,
> +'NODE_IPI_RPU_1'  : 64,
> +'NODE_IPI_PL_0'   : 65,
> +'NODE_IPI_PL_1'   : 66,
> +'NODE_IPI_PL_2'   : 67,
> +'NODE_IPI_PL_3'   : 68,
> +'NODE_PL' : 69,
> +'NODE_ID_MA'  : 70,
> +
> +'XILPM_RESET_PCIE_CFG' : 1000,
> +'XILPM_RESET_PCIE_BRIDGE'  : 1001,
> +'XILPM_RESET_PCIE_CTRL': 1002,
> +'XILPM_RESET_DP'   : 1003,
> +'XILPM_RESET_SWDT_CRF' : 1004,
> +'XILPM_RESET_AFI_FM5'  : 1005,
> +'XILPM_RESET_AFI_FM4'  : 1006,
> +'XILPM_RESET_AFI_FM3'  : 1007,
> +'XILPM_RESET_AFI_FM2'  : 1008,
> +'XILPM_RESET_AFI_FM1'  : 1009,
> +'XILPM_RESET_AFI_FM0'  : 1010,
> +'XILPM_RESET_GDMA' : 1011,
> +'XILPM_RESET_GPU_PP1'  : 1012,
> +'XILPM_RESET_GPU_PP0'  : 1013,
> +'XILPM_RESET_GPU'  : 10

Re: [U-Boot] [PATCH v3 2/2] arm64: zynqmp: add tool to convert PMU config object .c to binary

2019-05-03 Thread Luca Ceresoli 
Hi Michal,

On 04/05/19 00:31, Michal Simek wrote:
> Hi,
> 
> On 15. 04. 19 9:47, Luca Ceresoli wrote:
>> The recently-added ZYNQMP_LOAD_PM_CFG_OBJ_FILE option allows SPL to load a
>> PMUFW configuration object from a binary blob. However the configuration
>> object is produced by Xilinx proprietary tools as a C source file and no
>> tool exists to easily convert it to a binary blob in an embedded Linux
>> build system for U-Boot to use.
>>
>> Add a simple Python script to do the conversion.
>>
>> It is definitely not a complete C language parser, but it is enough to
>> parse the known patterns generated by Xilinx tools, including:
>>
>>  - defines
>>  - literal integers, optionally with a 'U' suffix
>>  - bitwise OR between them
>>
>> Signed-off-by: Luca Ceresoli 
>> ---
>>  arch/arm/mach-zynqmp/pm_cfg_obj_convert.py | 302 +
>>  1 file changed, 302 insertions(+)
>>  create mode 100755 arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
>>
>> diff --git a/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py 
>> b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
>> new file mode 100755
>> index ..5aea15860319
>> --- /dev/null
>> +++ b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
>> @@ -0,0 +1,302 @@
>> +#!/usr/bin/env python3
>> +# SPDX-License-Identifier: GPL-2.0+
>> +# Copyright (C) 2019 Luca Ceresoli 
>> +
>> +import sys
>> +import re
>> +import struct
>> +import logging
>> +import argparse
>> +
>> +parser = argparse.ArgumentParser(
>> +description='Convert a PMU configuration object from C source to a 
>> binary blob.',
>> +allow_abbrev=False)
>> +parser.add_argument('-D', '--debug', action="store_true")
>> +parser.add_argument(
>> +"in_file", metavar='INPUT_FILE',
>> +help='PMU configuration object (C source as produced by Xilinx XSDK)')
>> +parser.add_argument(
>> +"out_file", metavar='OUTPUT_FILE',
>> +help='PMU configuration object binary blob')
>> +args = parser.parse_args()
>> +
>> +logging.basicConfig(format='%(levelname)s:%(message)s',
>> +level=(logging.DEBUG if args.debug else 
>> logging.WARNING))
>> +
>> +pm_define = {
>> +'PM_CAP_ACCESS'   : 0x1,
>> +'PM_CAP_CONTEXT'  : 0x2,
>> +'PM_CAP_WAKEUP'   : 0x4,
>> +
>> +'NODE_UNKNOWN':  0,
>> +'NODE_APU':  1,
>> +'NODE_APU_0'  :  2,
>> +'NODE_APU_1'  :  3,
>> +'NODE_APU_2'  :  4,
>> +'NODE_APU_3'  :  5,
>> +'NODE_RPU':  6,
>> +'NODE_RPU_0'  :  7,
>> +'NODE_RPU_1'  :  8,
>> +'NODE_PLD':  9,
>> +'NODE_FPD': 10,
>> +'NODE_OCM_BANK_0' : 11,
>> +'NODE_OCM_BANK_1' : 12,
>> +'NODE_OCM_BANK_2' : 13,
>> +'NODE_OCM_BANK_3' : 14,
>> +'NODE_TCM_0_A': 15,
>> +'NODE_TCM_0_B': 16,
>> +'NODE_TCM_1_A': 17,
>> +'NODE_TCM_1_B': 18,
>> +'NODE_L2' : 19,
>> +'NODE_GPU_PP_0'   : 20,
>> +'NODE_GPU_PP_1'   : 21,
>> +'NODE_USB_0'  : 22,
>> +'NODE_USB_1'  : 23,
>> +'NODE_TTC_0'  : 24,
>> +'NODE_TTC_1'  : 25,
>> +'NODE_TTC_2'  : 26,
>> +'NODE_TTC_3'  : 27,
>> +'NODE_SATA'   : 28,
>> +'NODE_ETH_0'  : 29,
>> +'NODE_ETH_1'  : 30,
>> +'NODE_ETH_2'  : 31,
>> +'NODE_ETH_3'  : 32,
>> +'NODE_UART_0' : 33,
>> +'NODE_UART_1' : 34,
>> +'NODE_SPI_0'  : 35,
>> +'NODE_SPI_1'  : 36,
>> +'NODE_I2C_0'  : 37,
>> +'NODE_I2C_1'  : 38,
>> +'NODE_SD_0'   : 39,
>> +'NODE_SD_1'   : 40,
>> +'NODE_DP' : 41,
>> +'NODE_GDMA'   : 42,
>> +'NODE_ADMA'   : 43,
>> +'NODE_NAND'   : 44,
>> +'NODE_QSPI'   : 45,
>> +'NODE_GPIO'   : 46,
>> +'NODE_CAN_0'  : 47,
>> +'NODE_CAN_1'  : 48,
>> +'NODE_EXTERN' : 49,
>> +'NODE_APLL'   : 50,
>> +'NODE_VPLL'   : 51,
>> +'NODE_DPLL'   : 52,
>> +'NODE_RPLL'   : 53,
>> +'NODE_IOPLL'  : 54,
>> +'NODE_DDR': 55,
>> +'NODE_IPI_APU': 56,
>> +'NODE_IPI_RPU_0'  : 57,
>> +'NODE_GPU': 58,
>> +'NODE_PCIE'   : 59,
>> +'NODE_PCAP'   : 60,
>> +'NODE_RTC': 61,
>> +'NODE_LPD': 62,
>> +'NODE_VCU': 63,
>> +'NODE_IPI_RPU_1'  : 64,
>> +'NODE_IPI_PL_0'   : 65,
>> +'NODE_IPI_PL_1'   : 66,
>> +'NODE_IPI_PL_2'   : 67,
>> +'NODE_IPI_PL_3'   : 68,
>> +'NODE_PL' : 69,
>> +'NODE_ID_MA'  : 70,
>> +
>> +'XILPM_RESET_PCIE_CFG' : 1000,
>> +'XILPM_RESET_PCIE_BRIDGE'  : 1001,
>> +'XILPM_RESET_PCIE_CTRL': 1002,
>> +'XILPM_RESET_DP'   : 1003,
>> +'XILPM_RESET_SWDT_CRF' : 1004,
>> +'XILPM_RESET_AFI_FM5'  : 1005,
>> +'XILPM_RESET_AFI_FM4'  : 1006,
>> +'XILPM_RESET_AFI_FM3'  : 1007,
>> +'XILPM_RESET_AFI_FM2'  : 1008,
>> +'XILPM_RESET_AFI_FM1'  : 1009,
>> +'XILPM_RESET_AFI_FM0'

Re: [U-Boot] [PATCH v3 2/2] arm64: zynqmp: add tool to convert PMU config object .c to binary

2019-05-04 Thread Michal Simek 
Hi,

pá 3. 5. 2019 v 23:15 odesílatel Luca Ceresoli 
napsal:

> Hi Michal,
>
> On 04/05/19 00:31, Michal Simek wrote:
> > Hi,
> >
> > On 15. 04. 19 9:47, Luca Ceresoli wrote:
> >> The recently-added ZYNQMP_LOAD_PM_CFG_OBJ_FILE option allows SPL to
> load a
> >> PMUFW configuration object from a binary blob. However the configuration
> >> object is produced by Xilinx proprietary tools as a C source file and no
> >> tool exists to easily convert it to a binary blob in an embedded Linux
> >> build system for U-Boot to use.
> >>
> >> Add a simple Python script to do the conversion.
> >>
> >> It is definitely not a complete C language parser, but it is enough to
> >> parse the known patterns generated by Xilinx tools, including:
> >>
> >>  - defines
> >>  - literal integers, optionally with a 'U' suffix
> >>  - bitwise OR between them
> >>
> >> Signed-off-by: Luca Ceresoli 
> >> ---
> >>  arch/arm/mach-zynqmp/pm_cfg_obj_convert.py | 302 +
> >>  1 file changed, 302 insertions(+)
> >>  create mode 100755 arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> >>
> >> diff --git a/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> >> new file mode 100755
> >> index ..5aea15860319
> >> --- /dev/null
> >> +++ b/arch/arm/mach-zynqmp/pm_cfg_obj_convert.py
> >> @@ -0,0 +1,302 @@
> >> +#!/usr/bin/env python3
> >> +# SPDX-License-Identifier: GPL-2.0+
> >> +# Copyright (C) 2019 Luca Ceresoli 
> >> +
> >> +import sys
> >> +import re
> >> +import struct
> >> +import logging
> >> +import argparse
> >> +
> >> +parser = argparse.ArgumentParser(
> >> +description='Convert a PMU configuration object from C source to a
> binary blob.',
> >> +allow_abbrev=False)
> >> +parser.add_argument('-D', '--debug', action="store_true")
> >> +parser.add_argument(
> >> +"in_file", metavar='INPUT_FILE',
> >> +help='PMU configuration object (C source as produced by Xilinx
> XSDK)')
> >> +parser.add_argument(
> >> +"out_file", metavar='OUTPUT_FILE',
> >> +help='PMU configuration object binary blob')
> >> +args = parser.parse_args()
> >> +
> >> +logging.basicConfig(format='%(levelname)s:%(message)s',
> >> +level=(logging.DEBUG if args.debug else
> logging.WARNING))
> >> +
> >> +pm_define = {
> >> +'PM_CAP_ACCESS'   : 0x1,
> >> +'PM_CAP_CONTEXT'  : 0x2,
> >> +'PM_CAP_WAKEUP'   : 0x4,
> >> +
> >> +'NODE_UNKNOWN':  0,
> >> +'NODE_APU':  1,
> >> +'NODE_APU_0'  :  2,
> >> +'NODE_APU_1'  :  3,
> >> +'NODE_APU_2'  :  4,
> >> +'NODE_APU_3'  :  5,
> >> +'NODE_RPU':  6,
> >> +'NODE_RPU_0'  :  7,
> >> +'NODE_RPU_1'  :  8,
> >> +'NODE_PLD':  9,
> >> +'NODE_FPD': 10,
> >> +'NODE_OCM_BANK_0' : 11,
> >> +'NODE_OCM_BANK_1' : 12,
> >> +'NODE_OCM_BANK_2' : 13,
> >> +'NODE_OCM_BANK_3' : 14,
> >> +'NODE_TCM_0_A': 15,
> >> +'NODE_TCM_0_B': 16,
> >> +'NODE_TCM_1_A': 17,
> >> +'NODE_TCM_1_B': 18,
> >> +'NODE_L2' : 19,
> >> +'NODE_GPU_PP_0'   : 20,
> >> +'NODE_GPU_PP_1'   : 21,
> >> +'NODE_USB_0'  : 22,
> >> +'NODE_USB_1'  : 23,
> >> +'NODE_TTC_0'  : 24,
> >> +'NODE_TTC_1'  : 25,
> >> +'NODE_TTC_2'  : 26,
> >> +'NODE_TTC_3'  : 27,
> >> +'NODE_SATA'   : 28,
> >> +'NODE_ETH_0'  : 29,
> >> +'NODE_ETH_1'  : 30,
> >> +'NODE_ETH_2'  : 31,
> >> +'NODE_ETH_3'  : 32,
> >> +'NODE_UART_0' : 33,
> >> +'NODE_UART_1' : 34,
> >> +'NODE_SPI_0'  : 35,
> >> +'NODE_SPI_1'  : 36,
> >> +'NODE_I2C_0'  : 37,
> >> +'NODE_I2C_1'  : 38,
> >> +'NODE_SD_0'   : 39,
> >> +'NODE_SD_1'   : 40,
> >> +'NODE_DP' : 41,
> >> +'NODE_GDMA'   : 42,
> >> +'NODE_ADMA'   : 43,
> >> +'NODE_NAND'   : 44,
> >> +'NODE_QSPI'   : 45,
> >> +'NODE_GPIO'   : 46,
> >> +'NODE_CAN_0'  : 47,
> >> +'NODE_CAN_1'  : 48,
> >> +'NODE_EXTERN' : 49,
> >> +'NODE_APLL'   : 50,
> >> +'NODE_VPLL'   : 51,
> >> +'NODE_DPLL'   : 52,
> >> +'NODE_RPLL'   : 53,
> >> +'NODE_IOPLL'  : 54,
> >> +'NODE_DDR': 55,
> >> +'NODE_IPI_APU': 56,
> >> +'NODE_IPI_RPU_0'  : 57,
> >> +'NODE_GPU': 58,
> >> +'NODE_PCIE'   : 59,
> >> +'NODE_PCAP'   : 60,
> >> +'NODE_RTC': 61,
> >> +'NODE_LPD': 62,
> >> +'NODE_VCU': 63,
> >> +'NODE_IPI_RPU_1'  : 64,
> >> +'NODE_IPI_PL_0'   : 65,
> >> +'NODE_IPI_PL_1'   : 66,
> >> +'NODE_IPI_PL_2'   : 67,
> >> +'NODE_IPI_PL_3'   : 68,
> >> +'NODE_PL' : 69,
> >> +'NODE_ID_MA'  : 70,
> >> +
> >> +'XILPM_RESET_PCIE_CFG' : 1000,
> >> +'XILPM_RESET_PCIE_BRIDGE'  : 1001,
> >> +'XILPM_RESET_PCIE_CTRL': 1002,
> >> +'XILPM_RESET_D