Re: [U-Boot] [PATCH v3 2/3] spi: zynqmp_qspi: Add QSPI driver support for ZynqMP
On Thu, Oct 20, 2016 at 5:03 PM, S Durga Prasad Paladugu wrote: > Hi Jagan, > > On Wed, Jul 27, 2016 at 1:28 PM, Jagan Teki > wrote: >> >> On 19 July 2016 at 14:40, Siva Durga Prasad Paladugu >> wrote: >> > This adds QSPI driver support for ZynqMP platform >> > This driver supports all spi flash commands in >> > qspi single mode. >> > >> > Signed-off-by: Siva Durga Prasad Paladugu >> > --- >> > Changes for v3: >> > - None >> > Changes for v2: >> > - set no_all_quad as zynqmp qspi >> > controller doesnt support it >> > --- >> > drivers/spi/Kconfig | 9 + >> > drivers/spi/Makefile | 1 + >> > drivers/spi/zynqmp_qspi.c | 705 >> > ++ >> > 3 files changed, 715 insertions(+) >> > create mode 100644 drivers/spi/zynqmp_qspi.c >> > >> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig >> > index aca385d..6814ff9 100644 >> > --- a/drivers/spi/Kconfig >> > +++ b/drivers/spi/Kconfig >> > @@ -172,6 +172,15 @@ config ZYNQ_QSPI >> > Zynq QSPI IP core. This IP is used to connect the flash in >> > 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. >> > >> > +config ZYNQMP_QSPI >> > + bool "ZynqMP QSPI driver" >> > + depends on ARCH_ZYNQMP >> > + help >> > + Enable the ZynqMP Quad-SPI (QSPI) driver. This driver can be >> > + used to access the SPI NOR flash on platforms embedding this >> > + ZynqMP QSPI IP core. This IP is used to connect the flash in >> > + 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. >> >> If this is the case, spi couldn't be the correct place to handle nor >> dualness. > > > But i see zynq also added here. If this not the correct place could you > please point me > to where this should go. If you're sure to have this controller with SPI-NOR chips and will plan to add dual flash features in future then better write it on mtd/spi/ side (means flash side) thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/3] spi: zynqmp_qspi: Add QSPI driver support for ZynqMP
Hi Jagan, On Wed, Jul 27, 2016 at 1:28 PM, Jagan Teki wrote: > On 19 July 2016 at 14:40, Siva Durga Prasad Paladugu > wrote: > > This adds QSPI driver support for ZynqMP platform > > This driver supports all spi flash commands in > > qspi single mode. > > > > Signed-off-by: Siva Durga Prasad Paladugu > > --- > > Changes for v3: > > - None > > Changes for v2: > > - set no_all_quad as zynqmp qspi > > controller doesnt support it > > --- > > drivers/spi/Kconfig | 9 + > > drivers/spi/Makefile | 1 + > > drivers/spi/zynqmp_qspi.c | 705 ++ > > > 3 files changed, 715 insertions(+) > > create mode 100644 drivers/spi/zynqmp_qspi.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > > index aca385d..6814ff9 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -172,6 +172,15 @@ config ZYNQ_QSPI > > Zynq QSPI IP core. This IP is used to connect the flash in > > 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. > > > > +config ZYNQMP_QSPI > > + bool "ZynqMP QSPI driver" > > + depends on ARCH_ZYNQMP > > + help > > + Enable the ZynqMP Quad-SPI (QSPI) driver. This driver can be > > + used to access the SPI NOR flash on platforms embedding this > > + ZynqMP QSPI IP core. This IP is used to connect the flash in > > + 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. > > If this is the case, spi couldn't be the correct place to handle nor > dualness. > But i see zynq also added here. If this not the correct place could you please point me to where this should go. Regards, Siva > > thanks! > -- > Jagan. > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/3] spi: zynqmp_qspi: Add QSPI driver support for ZynqMP
On 19 July 2016 at 14:40, Siva Durga Prasad Paladugu wrote: > This adds QSPI driver support for ZynqMP platform > This driver supports all spi flash commands in > qspi single mode. > > Signed-off-by: Siva Durga Prasad Paladugu > --- > Changes for v3: > - None > Changes for v2: > - set no_all_quad as zynqmp qspi > controller doesnt support it > --- > drivers/spi/Kconfig | 9 + > drivers/spi/Makefile | 1 + > drivers/spi/zynqmp_qspi.c | 705 > ++ > 3 files changed, 715 insertions(+) > create mode 100644 drivers/spi/zynqmp_qspi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index aca385d..6814ff9 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -172,6 +172,15 @@ config ZYNQ_QSPI > Zynq QSPI IP core. This IP is used to connect the flash in > 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. > > +config ZYNQMP_QSPI > + bool "ZynqMP QSPI driver" > + depends on ARCH_ZYNQMP > + help > + Enable the ZynqMP Quad-SPI (QSPI) driver. This driver can be > + used to access the SPI NOR flash on platforms embedding this > + ZynqMP QSPI IP core. This IP is used to connect the flash in > + 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. If this is the case, spi couldn't be the correct place to handle nor dualness. thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/3] spi: zynqmp_qspi: Add QSPI driver support for ZynqMP
This adds QSPI driver support for ZynqMP platform
This driver supports all spi flash commands in
qspi single mode.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes for v3:
- None
Changes for v2:
- set no_all_quad as zynqmp qspi
controller doesnt support it
---
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/zynqmp_qspi.c | 705 ++
3 files changed, 715 insertions(+)
create mode 100644 drivers/spi/zynqmp_qspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index aca385d..6814ff9 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -172,6 +172,15 @@ config ZYNQ_QSPI
Zynq QSPI IP core. This IP is used to connect the flash in
4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+config ZYNQMP_QSPI
+ bool "ZynqMP QSPI driver"
+ depends on ARCH_ZYNQMP
+ help
+ Enable the ZynqMP Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ ZynqMP QSPI IP core. This IP is used to connect the flash in
+ 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+
config OMAP3_SPI
bool "McSPI driver for OMAP"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b1d9e20..4ea1266 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
+obj-$(CONFIG_ZYNQMP_QSPI) += zynqmp_qspi.o
diff --git a/drivers/spi/zynqmp_qspi.c b/drivers/spi/zynqmp_qspi.c
new file mode 100644
index 000..93ace51
--- /dev/null
+++ b/drivers/spi/zynqmp_qspi.c
@@ -0,0 +1,705 @@
+/*
+ * Xilinx ZynqMP Quad-SPI(QSPI) Controller Driver
+ *
+ * (C) Copyright 2016 Xilinx, Inc
+ * Siva Durga Prasad
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../mtd/spi/sf_internal.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * QSPI Config Register bit Masks
+ */
+#define ZYNQMP_QSPI_CONFIG_STRT_MODE_MASK BIT(29)
+#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASKGENMASK(31, 30)
+#define ZYNQMP_QSPI_CONFIG_DMA_MODEBIT(31)
+#define ZYNQMP_QSPI_CONFIG_CPHA_MASK BIT(2)
+#define ZYNQMP_QSPI_CONFIG_CPOL_MASK BIT(1)
+#define ZYNQMP_QSPI_CONFIG_GFIFO_WP_HOLD BIT(19)
+#define ZYNQMP_QSPI_CONFIG_BAUD_DIV_MASK GENMASK(5, 3)
+#define ZYNQMP_QSPI_CONFIG_DFLT_BAUD_RATE_DIV BIT(3)
+
+/*
+ * QSPI Interrupt Registers bit Masks
+ */
+#define ZYNQMP_QSPI_IXR_TXNFULL_MASK BIT(2)
+#define ZYNQMP_QSPI_IXR_TXFULL_MASKBIT(3)
+#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK BIT(4)
+#define ZYNQMP_QSPI_IXR_GFEMTY_MASKBIT(7)
+#define ZYNQMP_QSPI_IXR_ALL_MASK (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \
+ZYNQMP_QSPI_IXR_RXNEMTY_MASK)
+#define ZYNQMP_QSPI_GFIFO_ALL_INT_MASK 0xFBE
+
+/*
+ * QSPI Enable Register bit Masks
+ */
+#define ZYNQMP_QSPI_ENABLE_ENABLE_MASK BIT(0)
+
+/*
+ * QSPI Generic FIFO register bit masks
+ */
+#define ZYNQMP_QSPI_GFIFO_LOW_BUS BIT(14)
+#define ZYNQMP_QSPI_GFIFO_CS_LOWER BIT(12)
+#define ZYNQMP_QSPI_GFIFO_UP_BUS BIT(15)
+#define ZYNQMP_QSPI_GFIFO_CS_UPPER BIT(13)
+#define ZYNQMP_QSPI_GFIFO_SPI_MODE_QSPIGENMASK(11, 10)
+#define ZYNQMP_QSPI_GFIFO_SPI_MODE_SPI BIT(10)
+#define ZYNQMP_QSPI_GFIFO_TX BIT(16)
+#define ZYNQMP_QSPI_GFIFO_RX BIT(17)
+#define ZYNQMP_QSPI_GFIFO_STRIPE_MASK BIT(18)
+#define ZYNQMP_QSPI_GFIFO_IMD_MASK GENMASK(7, 0)
+#define ZYNQMP_QSPI_GFIFO_EXP_MASK BIT(9)
+#define ZYNQMP_QSPI_GFIFO_DATA_XFR_MASKBIT(8)
+
+#define ZYNQMP_QSPI_GFIFO_IMD_DATA_CS_ASSERT 5
+#define ZYNQMP_QSPI_GFIFO_IMD_DATA_CS_DEASSERT 5
+#define ZYNQMP_QSPI_GFIFO_EXP_INIT_VAL 8
+#define ZYNQMP_QSPI_GFIFO_IMD_MAX_DATA_LEN 255
+/*
+ * QSPI DMA Destination status register bit masks
+ */
+#define ZYNQMP_QSPI_DMA_DST_I_STS_DONE BIT(1)
+#define ZYNQMP_QSPI_DMA_DST_I_STS_MASK GENMASK(7, 1)
+
+/*
+ * QSPI Generic QSPI selection register bit mask
+ */
+#define ZYNQMP_QSPI_GQSPI_SELECT BIT(0)
+
+#define ZYNQMP_QSPI_FIFO_THRESHOLD 1
+
+#define SPI_XFER_ON_BOTH 0
+#define SPI_XFER_ON_LOWER 1
+#define SPI_XFER_ON_UPPER 2
+
+#define ZYNQMP_QSPI_DMA_ALIGN 0x4
+#define ZYNQMP_QSPI_DMA_POLL_TIMEOUT 1000
+
+#define ZYNQMP_QSPI_GENERIC_BASEADDR_OFFSET0x100
+#define ZYNQMP_QSPI_GENERIC_DMABASE_OFFSET 0x800
+
+/* QSPI register offsets */
+struct zynqmp_qspi_regs {
+ u32 confr; /* 0x00 */
+ u32 isr;/* 0x04 */
+ u32 ier;/* 0x08 */
+ u32 idisr; /* 0x0C */
+ u32 imaskr; /* 0x10 */
+ u32 enbr
