Re: [U-Boot] [PATCH v4 02/28] arm: socfpga: arria10: add sdram defines for Arria10

2017-02-17 Thread Ley Foon Tan 
On Mon, Jan 23, 2017 at 11:40 AM, Marek Vasut  wrote:
> On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
>> From: Tien Fong Chee 
>>
>> Add the structures for the SDRAM controller on Arria10.
>>
>> Signed-off-by: Dinh Nguyen 
>> Signed-off-by: Tien Fong Chee 
>> Cc: Marek Vasut 
>> Cc: Dinh Nguyen 
>> Cc: Chin Liang See 
>> Cc: Tien Fong 
>> ---
>>  arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 
>> +
>>  1 file changed, 380 insertions(+)
>>  create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
>> b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
>> new file mode 100644
>> index 000..0403531
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
>> @@ -0,0 +1,380 @@
>> +/*
>> + * Copyright (C) 2015 Altera Corporation 
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0
>> + */
>> +
>> +#ifndef  _SOCFPGA_SDRAM_A10_H_
>> +#define  _SOCFPGA_SDRAM_A10_H_
>
> #ifdef[space] and #define[space] , drop the [tab]
Okay
>
>> +#ifndef __ASSEMBLY__
>> +
>
>
> [...]
>
>> +#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM (1 << 30)
>
> Use the BIT(n) macro instead of (1 << n).
Okay

>
>> +#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM (1 << 29)
>> +#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM (1 << 28)
>> +#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM (1 << 27)
>
> [...]
>
> --
> Best regards,
> Marek Vasut
> ___
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Re: [U-Boot] [PATCH v4 02/28] arm: socfpga: arria10: add sdram defines for Arria10

2017-01-22 Thread Marek Vasut 
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> Add the structures for the SDRAM controller on Arria10.
> 
> Signed-off-by: Dinh Nguyen 
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
>  arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 
> +
>  1 file changed, 380 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
> b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
> new file mode 100644
> index 000..0403531
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
> @@ -0,0 +1,380 @@
> +/*
> + * Copyright (C) 2015 Altera Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0
> + */
> +
> +#ifndef  _SOCFPGA_SDRAM_A10_H_
> +#define  _SOCFPGA_SDRAM_A10_H_

#ifdef[space] and #define[space] , drop the [tab]

> +#ifndef __ASSEMBLY__
> +


[...]

> +#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM (1 << 30)

Use the BIT(n) macro instead of (1 << n).

> +#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM (1 << 29)
> +#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM (1 << 28)
> +#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM (1 << 27)

[...]

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH v4 02/28] arm: socfpga: arria10: add sdram defines for Arria10

2017-01-09 Thread Chee Tien Fong 
From: Tien Fong Chee 

Add the structures for the SDRAM controller on Arria10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SOCFPGA_SDRAM_A10_H_
+#define_SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 caltiming4;
+