Re: [U-Boot] [PATCH v5 19/19] arm: socfpga: agilex: Enable Agilex SoC build
On Wed, Oct 23, 2019 at 2:42 AM Simon Goldschmidt wrote: > > Am 11.10.2019 um 11:52 schrieb Ley Foon Tan: > > Add build support for Agilex SoC. > > > > Signed-off-by: Ley Foon Tan > > Reviewed-by: Simon Goldschmidt > > This does not apply any more, you'll need to rebase it (Marek has > changed mach-socfpga/Kconfig by renaming a board). > Okay, noted. Thanks. Regards Ley Foon > > > > --- > > v5: > > - Enable NCORE_CACHE > > > > v3: > > - Disable CONFIG_USE_TINY_PRINTF > > > > v2: > > - Remove IC_CLK define, use clock DM method to get i2c clock > > - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is > > enabled. > > --- > > arch/arm/Kconfig | 4 +- > > arch/arm/mach-socfpga/Kconfig | 16 ++ > > arch/arm/mach-socfpga/Makefile | 9 ++ > > configs/socfpga_agilex_defconfig | 59 +++ > > include/configs/socfpga_agilex_socdk.h | 207 + > > 5 files changed, 293 insertions(+), 2 deletions(-) > > create mode 100644 configs/socfpga_agilex_defconfig > > create mode 100644 include/configs/socfpga_agilex_socdk.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 3b0e315061..e6c9d19968 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -888,7 +888,7 @@ config ARCH_SOCFPGA > > bool "Altera SOCFPGA family" > > select ARCH_EARLY_INIT_R > > select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 > > - select ARM64 if TARGET_SOCFPGA_STRATIX10 > > + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX > > select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 > > select DM > > select DM_SERIAL > > @@ -900,7 +900,7 @@ config ARCH_SOCFPGA > > select SPL_LIBGENERIC_SUPPORT > > select SPL_NAND_SUPPORT if SPL_NAND_DENALI > > select SPL_OF_CONTROL > > - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 > > + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || > > TARGET_SOCFPGA_AGILEX > > select SPL_SERIAL_SUPPORT > > select SPL_SYSRESET > > select SPL_WATCHDOG_SUPPORT > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig > > index 1d914648e3..3f5c4b357f 100644 > > --- a/arch/arm/mach-socfpga/Kconfig > > +++ b/arch/arm/mach-socfpga/Kconfig > > @@ -26,6 +26,15 @@ config SYS_TEXT_BASE > > default 0x0140 if TARGET_SOCFPGA_ARRIA10 > > default 0x0140 if TARGET_SOCFPGA_GEN5 > > > > +config TARGET_SOCFPGA_AGILEX > > + bool > > + select ARMV8_MULTIENTRY > > + select ARMV8_SET_SMPEN > > + select ARMV8_SPIN_TABLE > > + select CLK > > + select NCORE_CACHE > > + select SPL_CLK if SPL > > + > > config TARGET_SOCFPGA_ARRIA5 > > bool > > select TARGET_SOCFPGA_GEN5 > > @@ -72,6 +81,10 @@ choice > > prompt "Altera SOCFPGA board select" > > optional > > > > +config TARGET_SOCFPGA_AGILEX_SOCDK > > + bool "Intel SOCFPGA SoCDK (Agilex)" > > + select TARGET_SOCFPGA_AGILEX > > + > > config TARGET_SOCFPGA_ARIES_MCVEVK > > bool "Aries MCVEVK (Cyclone V)" > > select TARGET_SOCFPGA_CYCLONE5 > > @@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT > > endchoice > > > > config SYS_BOARD > > + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > @@ -148,6 +162,7 @@ config SYS_BOARD > > default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA > > > > config SYS_VENDOR > > + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > @@ -165,6 +180,7 @@ config SYS_SOC > > default "socfpga" > > > > config SYS_CONFIG_NAME > > + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > > index 81b6ffc675..418f543b20 100644 > > --- a/arch/arm/mach-socfpga/Makefile > > +++ b/arch/arm/mach-socfpga/Makefile > > @@ -41,6 +41,14 @@ endif > > > > ifdef CONFIG_TARGET_SOCFPGA_AGILEX > > obj-y += clock_manager_agilex.o > > +obj-y+= mailbox_s10.o > > +obj-y+= misc_s10.o > > +obj-y+= mmu-arm64_s10.o > > +obj-y+= reset_manager_s10.o > > +obj-y+= system_manager_s10.o > > +obj-y+= timer_s10.o > > +obj-y+= wrap_pinmux_config_s10.o > > +obj-y+= wrap_pll_config_s10.o > > endif > > > > ifdef CONFIG_SPL_BUILD > > @@ -59,6 +67,7 @@ obj-
Re: [U-Boot] [PATCH v5 19/19] arm: socfpga: agilex: Enable Agilex SoC build
On Tue, Oct 22, 2019 at 3:02 PM Simon Goldschmidt wrote: > > On Fri, Oct 11, 2019 at 11:53 AM Ley Foon Tan wrote: > > > > Add build support for Agilex SoC. > > > > Signed-off-by: Ley Foon Tan > > Reviewed-by: Simon Goldschmidt > > > > --- > > v5: > > - Enable NCORE_CACHE > > > > v3: > > - Disable CONFIG_USE_TINY_PRINTF > > > > v2: > > - Remove IC_CLK define, use clock DM method to get i2c clock > > - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is > > enabled. > > --- > > arch/arm/Kconfig | 4 +- > > arch/arm/mach-socfpga/Kconfig | 16 ++ > > arch/arm/mach-socfpga/Makefile | 9 ++ > > configs/socfpga_agilex_defconfig | 59 +++ > > include/configs/socfpga_agilex_socdk.h | 207 + > > 5 files changed, 293 insertions(+), 2 deletions(-) > > create mode 100644 configs/socfpga_agilex_defconfig > > create mode 100644 include/configs/socfpga_agilex_socdk.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 3b0e315061..e6c9d19968 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -888,7 +888,7 @@ config ARCH_SOCFPGA > > bool "Altera SOCFPGA family" > > select ARCH_EARLY_INIT_R > > select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 > > - select ARM64 if TARGET_SOCFPGA_STRATIX10 > > + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX > > select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 > > select DM > > select DM_SERIAL > > @@ -900,7 +900,7 @@ config ARCH_SOCFPGA > > select SPL_LIBGENERIC_SUPPORT > > select SPL_NAND_SUPPORT if SPL_NAND_DENALI > > select SPL_OF_CONTROL > > - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 > > + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || > > TARGET_SOCFPGA_AGILEX > > select SPL_SERIAL_SUPPORT > > select SPL_SYSRESET > > select SPL_WATCHDOG_SUPPORT > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig > > index 1d914648e3..3f5c4b357f 100644 > > --- a/arch/arm/mach-socfpga/Kconfig > > +++ b/arch/arm/mach-socfpga/Kconfig > > @@ -26,6 +26,15 @@ config SYS_TEXT_BASE > > default 0x0140 if TARGET_SOCFPGA_ARRIA10 > > default 0x0140 if TARGET_SOCFPGA_GEN5 > > > > +config TARGET_SOCFPGA_AGILEX > > + bool > > + select ARMV8_MULTIENTRY > > + select ARMV8_SET_SMPEN > > + select ARMV8_SPIN_TABLE > > + select CLK > > + select NCORE_CACHE > > + select SPL_CLK if SPL > > + > > config TARGET_SOCFPGA_ARRIA5 > > bool > > select TARGET_SOCFPGA_GEN5 > > @@ -72,6 +81,10 @@ choice > > prompt "Altera SOCFPGA board select" > > optional > > > > +config TARGET_SOCFPGA_AGILEX_SOCDK > > + bool "Intel SOCFPGA SoCDK (Agilex)" > > + select TARGET_SOCFPGA_AGILEX > > + > > config TARGET_SOCFPGA_ARIES_MCVEVK > > bool "Aries MCVEVK (Cyclone V)" > > select TARGET_SOCFPGA_CYCLONE5 > > @@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT > > endchoice > > > > config SYS_BOARD > > + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > @@ -148,6 +162,7 @@ config SYS_BOARD > > default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA > > > > config SYS_VENDOR > > + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > @@ -165,6 +180,7 @@ config SYS_SOC > > default "socfpga" > > > > config SYS_CONFIG_NAME > > + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK > > default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK > > default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK > > default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > > index 81b6ffc675..418f543b20 100644 > > --- a/arch/arm/mach-socfpga/Makefile > > +++ b/arch/arm/mach-socfpga/Makefile > > @@ -41,6 +41,14 @@ endif > > > > ifdef CONFIG_TARGET_SOCFPGA_AGILEX > > obj-y += clock_manager_agilex.o > > +obj-y += mailbox_s10.o > > +obj-y += misc_s10.o > > +obj-y += mmu-arm64_s10.o > > +obj-y += reset_manager_s10.o > > +obj-y += system_manager_s10.o > > +obj-y += timer_s10.o > > +obj-y += wrap_pinmux_config_s10.o > > +obj-y += wrap_pll_config_s10.o > > endif > > > > ifdef CONFIG_SPL_BUILD > > @@ -59,6 +67,7 @@ obj-y += firewall.o > > obj-y += spl_s10.o > > endif > > ifdef CONFIG_TARGET_SOCFPGA_AGILEX > > +obj-y += firewall.o > > obj-y
Re: [U-Boot] [PATCH v5 19/19] arm: socfpga: agilex: Enable Agilex SoC build
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan: Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt This does not apply any more, you'll need to rebase it (Marek has changed mach-socfpga/Kconfig by renaming a board). Regards, Simon --- v5: - Enable NCORE_CACHE v3: - Disable CONFIG_USE_TINY_PRINTF v2: - Remove IC_CLK define, use clock DM method to get i2c clock - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is enabled. --- arch/arm/Kconfig | 4 +- arch/arm/mach-socfpga/Kconfig | 16 ++ arch/arm/mach-socfpga/Makefile | 9 ++ configs/socfpga_agilex_defconfig | 59 +++ include/configs/socfpga_agilex_socdk.h | 207 + 5 files changed, 293 insertions(+), 2 deletions(-) create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 include/configs/socfpga_agilex_socdk.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3b0e315061..e6c9d19968 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -888,7 +888,7 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_STRATIX10 + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL @@ -900,7 +900,7 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select SPL_SERIAL_SUPPORT select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1d914648e3..3f5c4b357f 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -26,6 +26,15 @@ config SYS_TEXT_BASE default 0x0140 if TARGET_SOCFPGA_ARRIA10 default 0x0140 if TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_AGILEX + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select ARMV8_SPIN_TABLE + select CLK + select NCORE_CACHE + select SPL_CLK if SPL + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -72,6 +81,10 @@ choice prompt "Altera SOCFPGA board select" optional +config TARGET_SOCFPGA_AGILEX_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex)" + select TARGET_SOCFPGA_AGILEX + config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -148,6 +162,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -165,6 +180,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 81b6ffc675..418f543b20 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -41,6 +41,14 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += mailbox_s10.o +obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += system_manager_s10.o +obj-y += timer_s10.o +obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_pll_config_s10.o endif ifdef CONFIG_SPL_BUILD @@ -59,6 +67,7 @@ obj-y += firewall.o obj-y += spl_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += firewall.o obj-y += spl_agilex.o endif endif diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig new file mode 100644 index 00..daf71ff0eb --- /dev/null +++ b/configs/socfpga_agilex_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CO
Re: [U-Boot] [PATCH v5 19/19] arm: socfpga: agilex: Enable Agilex SoC build
On Fri, Oct 11, 2019 at 11:53 AM Ley Foon Tan wrote: > > Add build support for Agilex SoC. > > Signed-off-by: Ley Foon Tan > Reviewed-by: Simon Goldschmidt > > --- > v5: > - Enable NCORE_CACHE > > v3: > - Disable CONFIG_USE_TINY_PRINTF > > v2: > - Remove IC_CLK define, use clock DM method to get i2c clock > - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is > enabled. > --- > arch/arm/Kconfig | 4 +- > arch/arm/mach-socfpga/Kconfig | 16 ++ > arch/arm/mach-socfpga/Makefile | 9 ++ > configs/socfpga_agilex_defconfig | 59 +++ > include/configs/socfpga_agilex_socdk.h | 207 + > 5 files changed, 293 insertions(+), 2 deletions(-) > create mode 100644 configs/socfpga_agilex_defconfig > create mode 100644 include/configs/socfpga_agilex_socdk.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 3b0e315061..e6c9d19968 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -888,7 +888,7 @@ config ARCH_SOCFPGA > bool "Altera SOCFPGA family" > select ARCH_EARLY_INIT_R > select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 > - select ARM64 if TARGET_SOCFPGA_STRATIX10 > + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX > select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 > select DM > select DM_SERIAL > @@ -900,7 +900,7 @@ config ARCH_SOCFPGA > select SPL_LIBGENERIC_SUPPORT > select SPL_NAND_SUPPORT if SPL_NAND_DENALI > select SPL_OF_CONTROL > - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 > + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || > TARGET_SOCFPGA_AGILEX > select SPL_SERIAL_SUPPORT > select SPL_SYSRESET > select SPL_WATCHDOG_SUPPORT > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig > index 1d914648e3..3f5c4b357f 100644 > --- a/arch/arm/mach-socfpga/Kconfig > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -26,6 +26,15 @@ config SYS_TEXT_BASE > default 0x0140 if TARGET_SOCFPGA_ARRIA10 > default 0x0140 if TARGET_SOCFPGA_GEN5 > > +config TARGET_SOCFPGA_AGILEX > + bool > + select ARMV8_MULTIENTRY > + select ARMV8_SET_SMPEN > + select ARMV8_SPIN_TABLE > + select CLK > + select NCORE_CACHE > + select SPL_CLK if SPL > + > config TARGET_SOCFPGA_ARRIA5 > bool > select TARGET_SOCFPGA_GEN5 > @@ -72,6 +81,10 @@ choice > prompt "Altera SOCFPGA board select" > optional > > +config TARGET_SOCFPGA_AGILEX_SOCDK > + bool "Intel SOCFPGA SoCDK (Agilex)" > + select TARGET_SOCFPGA_AGILEX > + > config TARGET_SOCFPGA_ARIES_MCVEVK > bool "Aries MCVEVK (Cyclone V)" > select TARGET_SOCFPGA_CYCLONE5 > @@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT > endchoice > > config SYS_BOARD > + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK > default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK > default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK > default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK > @@ -148,6 +162,7 @@ config SYS_BOARD > default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA > > config SYS_VENDOR > + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK > default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK > default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK > default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK > @@ -165,6 +180,7 @@ config SYS_SOC > default "socfpga" > > config SYS_CONFIG_NAME > + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK > default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK > default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK > default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > index 81b6ffc675..418f543b20 100644 > --- a/arch/arm/mach-socfpga/Makefile > +++ b/arch/arm/mach-socfpga/Makefile > @@ -41,6 +41,14 @@ endif > > ifdef CONFIG_TARGET_SOCFPGA_AGILEX > obj-y += clock_manager_agilex.o > +obj-y += mailbox_s10.o > +obj-y += misc_s10.o > +obj-y += mmu-arm64_s10.o > +obj-y += reset_manager_s10.o > +obj-y += system_manager_s10.o > +obj-y += timer_s10.o > +obj-y += wrap_pinmux_config_s10.o > +obj-y += wrap_pll_config_s10.o > endif > > ifdef CONFIG_SPL_BUILD > @@ -59,6 +67,7 @@ obj-y += firewall.o > obj-y += spl_s10.o > endif > ifdef CONFIG_TARGET_SOCFPGA_AGILEX > +obj-y += firewall.o > obj-y += spl_agilex.o > endif > endif > diff --git a/configs/socfpga_agilex_defconfig > b/configs/socfpga_agilex_defconfig > new file mode 100644 > index 00..daf71ff0eb > --- /dev/null > +++ b/configs/socfpga_agilex_defconfig > @@ -0,0 +1,59 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_SOCFPGA=y > +CONFIG_SYS_TEXT_BASE=0x100
[U-Boot] [PATCH v5 19/19] arm: socfpga: agilex: Enable Agilex SoC build
Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v5: - Enable NCORE_CACHE v3: - Disable CONFIG_USE_TINY_PRINTF v2: - Remove IC_CLK define, use clock DM method to get i2c clock - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is enabled. --- arch/arm/Kconfig | 4 +- arch/arm/mach-socfpga/Kconfig | 16 ++ arch/arm/mach-socfpga/Makefile | 9 ++ configs/socfpga_agilex_defconfig | 59 +++ include/configs/socfpga_agilex_socdk.h | 207 + 5 files changed, 293 insertions(+), 2 deletions(-) create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 include/configs/socfpga_agilex_socdk.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3b0e315061..e6c9d19968 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -888,7 +888,7 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_STRATIX10 + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL @@ -900,7 +900,7 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select SPL_SERIAL_SUPPORT select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1d914648e3..3f5c4b357f 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -26,6 +26,15 @@ config SYS_TEXT_BASE default 0x0140 if TARGET_SOCFPGA_ARRIA10 default 0x0140 if TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_AGILEX + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select ARMV8_SPIN_TABLE + select CLK + select NCORE_CACHE + select SPL_CLK if SPL + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -72,6 +81,10 @@ choice prompt "Altera SOCFPGA board select" optional +config TARGET_SOCFPGA_AGILEX_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex)" + select TARGET_SOCFPGA_AGILEX + config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -148,6 +162,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -165,6 +180,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 81b6ffc675..418f543b20 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -41,6 +41,14 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += mailbox_s10.o +obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += system_manager_s10.o +obj-y += timer_s10.o +obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_pll_config_s10.o endif ifdef CONFIG_SPL_BUILD @@ -59,6 +67,7 @@ obj-y += firewall.o obj-y += spl_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += firewall.o obj-y += spl_agilex.o endif endif diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig new file mode 100644 index 00..daf71ff0eb --- /dev/null +++ b/configs/socfpga_agilex_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_BOOTDELAY=5 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_A
