Re: [U-Boot] [PATCH v5 2/3] apf27: add support for the armadeus APF27 board
Hallo Philippe,
On 27/08/2013 19:12, Philippe Reynes wrote:
Signed-off-by: Philippe Reynes trem...@yahoo.fr
Signed-off-by: Eric Jarrige eric.jarr...@armadeus.org
Signed-off-by: Nicolas Colombain nicolas.colomb...@armadeus.com
---
MAINTAINERS |5 +
board/armadeus/apf27/Makefile| 30 ++
board/armadeus/apf27/apf27.c | 252 +
board/armadeus/apf27/apf27.h | 489
++
board/armadeus/apf27/lowlevel_init.S | 168
boards.cfg |1 +
include/configs/apf27.h | 374 ++
7 files changed, 1319 insertions(+), 0 deletions(-)
create mode 100644 board/armadeus/apf27/Makefile
create mode 100644 board/armadeus/apf27/apf27.c
create mode 100644 board/armadeus/apf27/apf27.h
create mode 100644 board/armadeus/apf27/lowlevel_init.S
create mode 100644 include/configs/apf27.h
IMHO patches are good - only minor comments.
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd-ram_size */
+ if (get_num_ram_bank() 1) {
+ gd-ram_size = PHYS_SDRAM_2 - CONFIG_SYS_SDRAM_BASE
+ + get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ } else {
+ gd-ram_size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
Last time I asked if it is possible to use get_ram_size() twice to get
the whole size. Which is the result ?
+ }
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ phys_size_t ramsize = gd-ram_size;
+
+ if (get_num_ram_bank() 1)
+ ramsize -= PHYS_SDRAM_2 - CONFIG_SYS_SDRAM_BASE;
+
+ gd-bd-bi_dram[0].start = PHYS_SDRAM_1;
+ gd-bd-bi_dram[0].size = ramsize;
+ gd-bd-bi_dram[1].start = PHYS_SDRAM_2;
+ if (get_num_ram_bank() 1)
+ gd-bd-bi_dram[1].size = ramsize;
+ else
Having twice the branch with if (get_num_ram_bank() 1) looks
confusing. You could avoid the first one and write directly here the result.
+void board_init_f(ulong bootflag)
+{
+ /*
+ * copy ourselves from where we are running to where we were
+ * linked at. Use ulong pointers as all addresses involved
+ * are 4-byte-aligned.
+ */
+ ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
+ asm volatile (ldr %0, =_start : =r(start_ptr));
+ asm volatile (ldr %0, =_end : =r(end_ptr));
+ asm volatile (ldr %0, =board_init_f : =r(link_ptr));
+ asm volatile (adr %0, board_init_f : =r(run_ptr));
+ for (dst = start_ptr; dst end_ptr; dst++)
+ *dst = *(dst+(run_ptr-link_ptr));
+
+ /*
+ * branch to nand_boot's link-time address.
+ */
+ asm volatile(ldr pc, =nand_boot);
+}
ok, we are in sync with other boards !
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h
new file mode 100644
index 000..64e7e4d
--- /dev/null
+++ b/board/armadeus/apf27/apf27.h
@@ -0,0 +1,489 @@
+/*
+ * Copyright (C) 2008-2013 Eric Jarrige eric.jarr...@armadeus.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __APF27_H
+#define __APF27_H
+
+/* FPGA program pin configuration */
+#define ACFG_FPGA_PWR(GPIO_PORTF | 19) /* FPGA prog pin */
+#define ACFG_FPGA_PRG(GPIO_PORTF | 11) /* FPGA prog pin */
+#define ACFG_FPGA_CLK(GPIO_PORTF | 15) /* FPGA clk pin */
+#define ACFG_FPGA_RDATA 0xD600 /* FPGA data addr */
+#define ACFG_FPGA_WDATA 0xD600 /* FPGA data addr */
+#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
+#define ACFG_FPGA_DONE (GPIO_PORTF | 9)/* FPGA done pin */
+#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
+#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
+#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
+#define ACFG_FPGA_RESET (GPIO_PORTF | 7)/* FPGA done pin */
+
+/* MMC pin */
+#define PC_PWRON (GPIO_PORTF | 16)
+
+/*
+ * MPU CLOCK source before PLL
+ * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
+ */
+#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
+#define ACFG_MPCTL1_VAL 0
+#define CONFIG_MPLL_FREQ 399
+
+#define ACFG_CLK_FREQ(CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
+
+/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
+#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
+#define ACFG_SPCTL1_VAL 0
+#define CONFIG_SPLL_FREQ 300 /* MHz */
+
+/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
+#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
+
+/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
+#define CONFIG_HCLK_FREQ 133
[U-Boot] [PATCH v5 2/3] apf27: add support for the armadeus APF27 board
Signed-off-by: Philippe Reynes trem...@yahoo.fr
Signed-off-by: Eric Jarrige eric.jarr...@armadeus.org
Signed-off-by: Nicolas Colombain nicolas.colomb...@armadeus.com
---
MAINTAINERS |5 +
board/armadeus/apf27/Makefile| 30 ++
board/armadeus/apf27/apf27.c | 252 +
board/armadeus/apf27/apf27.h | 489 ++
board/armadeus/apf27/lowlevel_init.S | 168
boards.cfg |1 +
include/configs/apf27.h | 374 ++
7 files changed, 1319 insertions(+), 0 deletions(-)
create mode 100644 board/armadeus/apf27/Makefile
create mode 100644 board/armadeus/apf27/apf27.c
create mode 100644 board/armadeus/apf27/apf27.h
create mode 100644 board/armadeus/apf27/lowlevel_init.S
create mode 100644 include/configs/apf27.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a900dc..abf8380 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -716,6 +716,11 @@ Ilko Iliev il...@ronetix.at
PM9263 AT91SAM9263
PM9G45 ARM926EJS (AT91SAM9G45 SoC)
+Eric Jarrige eric.jarr...@armadeus.org
+Philippe Reynes trem...@yahoo.fr
+
+ apf27 ARM926EJS (i.MX27 SoC)
+
Michael Jones michael.jo...@matrix-vision.de
omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
new file mode 100644
index 000..ec0cb03
--- /dev/null
+++ b/board/armadeus/apf27/Makefile
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+# (C) Copyright 2012-2013
+# Eric Jarrige eric.jarr...@armadeus.org
+#
+# SPDX-License-Identifier:GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := apf27.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.S)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
new file mode 100644
index 000..98c51a7
--- /dev/null
+++ b/board/armadeus/apf27/apf27.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2008-2013 Eric Jarrige eric.jarr...@armadeus.org
+ *
+ * based on the files by
+ * Sascha Hauer, Pengutronix
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include environment.h
+#include jffs2/jffs2.h
+#include nand.h
+#include netdev.h
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/arch/gpio.h
+#include asm/gpio.h
+#include asm/errno.h
+#include apf27.h
+#include crc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fuse bank 1 row 8 is reserved for future use and therefore available for
+ * customer use. The APF27 board uses this fuse to store the board revision:
+ * 0: initial board revision
+ * 1: first revision - Presence of the second RAM chip on the board is blown in
+ * fuse bank 1 row 9 bit 0 - No hardware change
+ * N: to be defined
+ */
+static u32 get_board_rev(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+
+ return readl(iim-bank[1].fuse_regs[8]);
+}
+
+/*
+ * Fuse bank 1 row 9 is reserved for future use and therefore available for
+ * customer use. The APF27 board revision 1 uses the bit 0 to permanently store
+ * the presence of the second RAM chip
+ * 0: AFP27 with 1 RAM of 64 MiB
+ * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
+ */
+static int get_num_ram_bank(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ int nr_dram_banks = 1;
+
+ if ((get_board_rev() 0) (CONFIG_NR_DRAM_BANKS 1))
+ nr_dram_banks += readl(iim-bank[1].fuse_regs[9]) 0x01;
+ else
+ nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
+
+ return nr_dram_banks;
+}
+
+static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
+ u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
+ u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
+ u32 puen, u32 gius)
+{
+ struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
+
+ writel(gpio_dr, regs-port[port].gpio_dr);
+ writel(ocr1, regs-port[port].ocr1);
+ writel(ocr2, regs-port[port].ocr2);
+ writel(iconfa1, regs-port[port].iconfa1);
+ writel(iconfa2, regs-port[port].iconfa2);
+ writel(iconfb1, regs-port[port].iconfb1);
+ writel(iconfb2, regs-port[port].iconfb2);
+ writel(icr1, regs-port[port].icr1);
+ writel(icr2, regs-port[port].icr2);
+ writel(imr, regs-port[port].imr);
+
