This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Hans de Goede
Signed-off-by: Ma Haijun
Signed-off-by: Oliver Schinagl
Signed-off-by: Henrik Nordström
Signed-off-by: Ian Campbell
Reviewed-by: Tom Rini
Acked-by: Marek Vasut
Cc: Stefan Roese
Cc: Tom Cubie
---
v5: Based on 3f5ff92b1503 "sunxi: add comments to pll1_para array."
- No changes required
v4: Based on d9fe0a1e061e "sunxi: mksunxiboot: remove unnecessary casts."
- No changes required
v3: Based on c89867dca2e9 "sunxi: clocks: clock_get_pll5
prototype and coding style".
v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c "sunxi: mmc:
checkpatch whitespace fixes" with v2014.04-rc2 merged in:
- Additional pin definitions
v1: Based on u-boot-sunxi.git#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash
section in ldscripts" vs v2014.01.
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/pinmux.c | 61 ++
arch/arm/include/asm/arch-sunxi/gpio.h | 147 +
3 files changed, 209 insertions(+)
create mode 100644 arch/arm/cpu/armv7/sunxi/pinmux.c
create mode 100644 arch/arm/include/asm/arch-sunxi/gpio.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 440d266..529e7ec 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -9,4 +9,5 @@
#
obj-y += timer.o
obj-y += clock.o
+obj-y += pinmux.o
obj-$(CONFIG_SUN7I)+= clock_sun4i.o
diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c
b/arch/arm/cpu/armv7/sunxi/pinmux.c
new file mode 100644
index 000..1f2843f
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd.
+ * Tom Cubie
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ u32 index = GPIO_CFG_INDEX(pin);
+ u32 offset = GPIO_CFG_OFFSET(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
+
+ return 0;
+}
+
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+ u32 cfg;
+ u32 bank = GPIO_BANK(pin);
+ u32 index = GPIO_CFG_INDEX(pin);
+ u32 offset = GPIO_CFG_OFFSET(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ cfg = readl(&pio->cfg[0] + index);
+ cfg >>= offset;
+
+ return cfg & 0xf;
+}
+
+int sunxi_gpio_set_drv(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ u32 index = GPIO_DRV_INDEX(pin);
+ u32 offset = GPIO_DRV_OFFSET(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
+
+ return 0;
+}
+
+int sunxi_gpio_set_pull(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ u32 index = GPIO_PULL_INDEX(pin);
+ u32 offset = GPIO_PULL_OFFSET(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
new file mode 100644
index 000..892479c
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd.
+ * Tom Cubie
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GPIO_H
+#define _SUNXI_GPIO_H
+
+#include
+
+/*
+ * sunxi has 9 banks of gpio, they are:
+ * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
+ * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
+ * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
+ */
+
+#define SUNXI_GPIO_A 0
+#define SUNXI_GPIO_B 1
+#define SUNXI_GPIO_C 2
+#define SUNXI_GPIO_D 3
+#define SUNXI_GPIO_E 4
+#define SUNXI_GPIO_F 5
+#define SUNXI_GPIO_G 6
+#define SUNXI_GPIO_H 7
+#define SUNXI_GPIO_I 8
+#define SUNXI_GPIO_BANKS 9
+
+struct sunxi_gpio {
+ u32 cfg[4];
+ u32 dat;
+ u32 drv[2];
+ u32 pull[2];
+};
+
+/* gpio interrupt control */
+struct sunxi_gpio_int {
+ u32 cfg[3];
+ u32 ctl;
+ u32 sta;
+ u32 deb;/* interrupt debounce */
+};
+
+struct sunxi_gpio_reg {
+ struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
+ u8 res[0xbc];
+ struct sunxi_gpio_int gpio_int;
+};
+
+#define BANK_TO_GPIO(bank) \
+ &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]
+
+#define GPIO_BANK(pin) ((pin) >> 5)
+#define GPIO_NUM(pin) ((pin) & 0x1f)
+
+#define GPIO_CFG_INDEX(pin)(((pin) & 0x1f) >> 3)
+#define GPIO_CFG_OFFSET(pin) pin) & 0x1f) & 0x7) << 2)
+
+#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4)
+#def
