Re: [U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

2015-03-24 Thread York Sun 


On 03/23/2015 06:34 PM, Scott Wood wrote:
 On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
 +Generage NAND image
 +---
 +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
 +Append u-boot-with-spl.bin after RCW image. The RCW image should
 +have these PBI commands
 +
 +1) CCSR 4-byte write to 0x00e00404, data=0x
 +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
 +3) Block Copy: SRC=0x0104, SRC_ADDR=0x00c0, DEST_ADDR=0x1800a000,
 +BLOCK_SIZE=0x00014000
 
 The RCW source should probably be 0x107, not 0x104.  Bit 0x002 requests
 first/last bad block markers rather than first/second, and bit 0x001
 enables ECC.  Also, this documentation is LS2085A-specific (most of it
 will probably apply to all chips with this chassis), not RDB or QDS
 specific, with the exception of the RCW source ID which depends on the
 specific NAND chip.  It would be better to put it in one place rather
 than duplicate it, with a table of RCW source IDs for each board.
 
 Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
 for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
 RCW source to be 0x111.
 

I will try your suggestion. I use the value from the original RCW we created
during bring-up. Oddly it still works if it is wrong.

York
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Re: [U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

2015-03-24 Thread prabha...@freescale.com 

 -Original Message-
 From: Sun York-R58495
 Sent: Tuesday, March 24, 2015 9:15 PM
 To: Wood Scott-B07421
 Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579
 Subject: Re: [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support
 
 
 
 On 03/23/2015 06:34 PM, Scott Wood wrote:
  On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
  +Generage NAND image
  +---
  +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
  +Append u-boot-with-spl.bin after RCW image. The RCW image should
  +have these PBI commands
  +
  +1) CCSR 4-byte write to 0x00e00404, data=0x
  +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
  +3) Block Copy: SRC=0x0104, SRC_ADDR=0x00c0,
  +DEST_ADDR=0x1800a000,
  +BLOCK_SIZE=0x00014000
 
  The RCW source should probably be 0x107, not 0x104.  Bit 0x002
  requests first/last bad block markers rather than first/second, and
  bit 0x001 enables ECC.  Also, this documentation is LS2085A-specific
  (most of it will probably apply to all chips with this chassis), not
  RDB or QDS specific, with the exception of the RCW source ID which
  depends on the specific NAND chip.  It would be better to put it in
  one place rather than duplicate it, with a table of RCW source IDs for each
 board.
 
  Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
  for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
  RCW source to be 0x111.
 
 
for RDB. I think RCW source should be 0x119. 
bad block at first/last page(ONFI requirement) and 4bit ECC

-prabhakar


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Re: [U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

2015-03-24 Thread Scott Wood 
On Tue, 2015-03-24 at 11:34 -0500, Kushwaha Prabhakar-B32579 wrote:
 
  -Original Message-
  From: Sun York-R58495
  Sent: Tuesday, March 24, 2015 9:15 PM
  To: Wood Scott-B07421
  Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579
  Subject: Re: [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support
  
  
  
  On 03/23/2015 06:34 PM, Scott Wood wrote:
   On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
   +Generage NAND image
   +---
   +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
   +Append u-boot-with-spl.bin after RCW image. The RCW image should
   +have these PBI commands
   +
   +1) CCSR 4-byte write to 0x00e00404, data=0x
   +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
   +3) Block Copy: SRC=0x0104, SRC_ADDR=0x00c0,
   +DEST_ADDR=0x1800a000,
   +BLOCK_SIZE=0x00014000
  
   The RCW source should probably be 0x107, not 0x104.  Bit 0x002
   requests first/last bad block markers rather than first/second, and
   bit 0x001 enables ECC.  Also, this documentation is LS2085A-specific
   (most of it will probably apply to all chips with this chassis), not
   RDB or QDS specific, with the exception of the RCW source ID which
   depends on the specific NAND chip.  It would be better to put it in
   one place rather than duplicate it, with a table of RCW source IDs for 
   each
  board.
  
   Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
   for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
   RCW source to be 0x111.
  
  
 for RDB. I think RCW source should be 0x119. 
 bad block at first/last page(ONFI requirement) and 4bit ECC

Yes, sorry.

-Scott


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Re: [U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

2015-03-24 Thread York Sun 


On 03/24/2015 09:34 AM, Kushwaha Prabhakar-B32579 wrote:
 
 -Original Message-
 From: Sun York-R58495
 Sent: Tuesday, March 24, 2015 9:15 PM
 To: Wood Scott-B07421
 Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579
 Subject: Re: [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support



 On 03/23/2015 06:34 PM, Scott Wood wrote:
 On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
 +Generage NAND image
 +---
 +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
 +Append u-boot-with-spl.bin after RCW image. The RCW image should
 +have these PBI commands
 +
 +1) CCSR 4-byte write to 0x00e00404, data=0x
 +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
 +3) Block Copy: SRC=0x0104, SRC_ADDR=0x00c0,
 +DEST_ADDR=0x1800a000,
 +BLOCK_SIZE=0x00014000

 The RCW source should probably be 0x107, not 0x104.  Bit 0x002
 requests first/last bad block markers rather than first/second, and
 bit 0x001 enables ECC.  Also, this documentation is LS2085A-specific
 (most of it will probably apply to all chips with this chassis), not
 RDB or QDS specific, with the exception of the RCW source ID which
 depends on the specific NAND chip.  It would be better to put it in
 one place rather than duplicate it, with a table of RCW source IDs for each
 board.

 Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
 for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
 RCW source to be 0x111.


 for RDB. I think RCW source should be 0x119. 
 bad block at first/last page(ONFI requirement) and 4bit ECC
 

I think 0x119 is correct. It is the same value I read back from rcw_src. I just
verified it boots OK. I have been using 0x104 as the source id incorrectly but
it also boots.

York

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Re: [U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

2015-03-23 Thread Scott Wood 
On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
 +Generage NAND image
 +---
 +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig.
 +Append u-boot-with-spl.bin after RCW image. The RCW image should
 +have these PBI commands
 +
 +1) CCSR 4-byte write to 0x00e00404, data=0x
 +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
 +3) Block Copy: SRC=0x0104, SRC_ADDR=0x00c0, DEST_ADDR=0x1800a000,
 +BLOCK_SIZE=0x00014000

The RCW source should probably be 0x107, not 0x104.  Bit 0x002 requests
first/last bad block markers rather than first/second, and bit 0x001
enables ECC.  Also, this documentation is LS2085A-specific (most of it
will probably apply to all chips with this chassis), not RDB or QDS
specific, with the exception of the RCW source ID which depends on the
specific NAND chip.  It would be better to put it in one place rather
than duplicate it, with a table of RCW source IDs for each board.

Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is
for a 2K-page NAND chip.  RDB has a 4K-page NAND, so I think you want
RCW source to be 0x111.

-Scott


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[U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support

2015-03-20 Thread York Sun 
From: Scott Wood scottw...@freescale.com

This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: York Sun york...@freescale.com

---

Changes in v5:
  Update LS2085AQDS README to include instructions to form NAND image

Changes in v4:
  Update MAINTAINERS file

Changes in v3: None
Changes in v2: None

 arch/arm/Kconfig |1 +
 arch/arm/cpu/armv8/fsl-lsch3/soc.c   |   48 
 arch/arm/cpu/armv8/u-boot-spl.lds|   77 ++
 arch/arm/include/asm/arch-fsl-lsch3/config.h |9 +++
 arch/arm/lib/crt0_64.S   |7 +++
 board/freescale/ls2085aqds/MAINTAINERS   |1 +
 board/freescale/ls2085aqds/README|   19 +++
 board/freescale/ls2085aqds/ddr.c |4 ++
 common/spl/spl.c |2 +-
 common/spl/spl_nand.c|2 +-
 configs/ls2085aqds_nand_defconfig|4 ++
 drivers/misc/fsl_ifc.c   |   12 
 drivers/mtd/nand/fsl_ifc_spl.c   |2 +-
 include/configs/ls2085a_common.h |   29 ++
 include/configs/ls2085aqds.h |   50 +++--
 15 files changed, 259 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/u-boot-spl.lds
 create mode 100644 configs/ls2085aqds_nand_defconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6ba4b8d..f73541c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -652,6 +652,7 @@ config TARGET_LS2085AQDS
bool Support ls2085aqds
select ARM64
select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
help
  Support for Freescale LS2085AQDS platform
  The LS2085A Development System (QDS) is a high-performance
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c 
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 17700ef..ca00108 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -6,8 +6,13 @@
 
 #include common.h
 #include fsl_ifc.h
+#include nand.h
+#include spl.h
 #include asm/arch-fsl-lsch3/soc.h
 #include asm/io.h
+#include asm/global_data.h
+
+DECLARE_GLOBAL_DATA_PTR;
 
 static void erratum_a008751(void)
 {
@@ -18,8 +23,51 @@ static void erratum_a008751(void)
 #endif
 }
 
+static void erratum_rcw_src(void)
+{
+#if defined(CONFIG_SPL)
+   u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+   u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
+   u32 val;
+
+   val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+   val = ~DCFG_PORSR1_RCW_SRC;
+   val |= DCFG_PORSR1_RCW_SRC_NOR;
+   out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
+#endif
+}
+
 void fsl_lsch3_early_init_f(void)
 {
erratum_a008751();
+   erratum_rcw_src();
init_early_memctl_regs();   /* tighten IFC timing */
 }
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+   /* Clear global data */
+   memset((void *)gd, 0, sizeof(gd_t));
+
+   arch_cpu_init();
+   board_early_init_f();
+   timer_init();
+   env_init();
+   gd-baudrate = getenv_ulong(baudrate, 10, CONFIG_BAUDRATE);
+
+   serial_init();
+   console_init_f();
+   dram_init();
+
+   /* Clear the BSS. */
+   memset(__bss_start, 0, __bss_end - __bss_start);
+
+   board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+   return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds 
b/arch/arm/cpu/armv8/u-boot-spl.lds
new file mode 100644
index 000..4df339c
--- /dev/null
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2013
+ * David Feng feng...@phytium.com.cn
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, www.ti.com
+ * Aneesh V ane...@ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+   LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+   LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT(elf64-littleaarch64, elf64-littleaarch64, 
elf64-littleaarch64)
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+   .text : {
+   . = ALIGN(8);
+   *(.__image_copy_start)
+   CPUDIR/start.o (.text*)
+   *(.text*)
+   } .sram
+
+   .rodata : {
+   . = ALIGN(8);
+   *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+   } .sram
+
+   .data : {
+   . = ALIGN(8);
+   *(.data*)
+   } .sram
+
+   .u_boot_list : {
+   . = ALIGN(8);
+   KEEP(*(SORT(.u_boot_list*)));
+   } .sram
+
+   .image_copy_end : {
+   . = ALIGN(8);
+   *(.__image_copy_end)