Re: [U-Boot] [PATCH v5 4/8] arm: mx5: Add more register definitions

2017-11-09 Thread Stefano Babic 
On 08/11/2017 16:35, Martyn Welch wrote:
> Add register definitions require for video configuration.
> 
> Signed-off-by: Nandor Han 
> Signed-off-by: Martyn Welch 
> Reviewed-by: Stefano Babic 
> Cc: Stefano Babic 
> ---
> Changes in v5:
>   - Reduced checkpatch warnings.
> 
>  arch/arm/include/asm/arch-mx5/crm_regs.h |  8 
>  arch/arm/include/asm/arch-mx5/imx-regs.h | 33 
> 
>  2 files changed, 41 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h 
> b/arch/arm/include/asm/arch-mx5/crm_regs.h
> index b61c7b9..7fea569 100644
> --- a/arch/arm/include/asm/arch-mx5/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
> @@ -210,6 +210,14 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL  (0x1 << 1)
>  #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL  0x1
>  
> +/* Define the bits in register CSCMR2 */
> +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET26
> +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK  (0x7 << 26)
> +#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v)(((v) & 0x7) << 26)
> +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7)
> +
> +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
> +
>  /* Define the bits in register CSCDR2 */
>  #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET  25
>  #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK(0x7 << 25)
> diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
> b/arch/arm/include/asm/arch-mx5/imx-regs.h
> index 2b0dc1e..61c8d44 100644
> --- a/arch/arm/include/asm/arch-mx5/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
> @@ -416,6 +416,39 @@ struct iomuxc {
>  };
>  #endif
>  
> +#define IOMUXC_GPR2_BITMAP_SPWG  0
> +#define IOMUXC_GPR2_BITMAP_JEIDA 1
> +
> +#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET   6
> +#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << 
> IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
> +#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA(IOMUXC_GPR2_BITMAP_JEIDA << \
> +  
> IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
> +#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \
> +  
> IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
> +
> +#define IOMUXC_GPR2_DATA_WIDTH_180
> +#define IOMUXC_GPR2_DATA_WIDTH_241
> +
> +#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET5
> +#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK  (1 << 
> IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
> +#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \
> +  
> IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
> +#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \
> +  
> IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
> +
> +#define IOMUXC_GPR2_MODE_DISABLED0
> +#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
> +#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
> +
> +#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
> +#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK   (3 << 
> IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
> +#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED   (IOMUXC_GPR2_MODE_DISABLED << \
> +  
> IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
> +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
> (IOMUXC_GPR2_MODE_ENABLED_DI0 << \
> +  
> IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
> +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1
> (IOMUXC_GPR2_MODE_ENABLED_DI1 << \
> +  
> IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
> +
>  /* System Reset Controller (SRC) */
>  struct src {
>   u32 scr;
> 

Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic

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[U-Boot] [PATCH v5 4/8] arm: mx5: Add more register definitions

2017-11-08 Thread Martyn Welch 
Add register definitions require for video configuration.

Signed-off-by: Nandor Han 
Signed-off-by: Martyn Welch 
Reviewed-by: Stefano Babic 
Cc: Stefano Babic 
---
Changes in v5:
  - Reduced checkpatch warnings.

 arch/arm/include/asm/arch-mx5/crm_regs.h |  8 
 arch/arm/include/asm/arch-mx5/imx-regs.h | 33 
 2 files changed, 41 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h 
b/arch/arm/include/asm/arch-mx5/crm_regs.h
index b61c7b9..7fea569 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -210,6 +210,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL(0x1 << 1)
 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL0x1
 
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET  26
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK(0x7 << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v)  (((v) & 0x7) << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r)   (((r) >> 26) & 0x7)
+
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
+
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET25
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK  (0x7 << 25)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 2b0dc1e..61c8d44 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -416,6 +416,39 @@ struct iomuxc {
 };
 #endif
 
+#define IOMUXC_GPR2_BITMAP_SPWG0
+#define IOMUXC_GPR2_BITMAP_JEIDA   1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK   (1 << 
IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA  (IOMUXC_GPR2_BITMAP_JEIDA << \
+
IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG   (IOMUXC_GPR2_BITMAP_SPWG << \
+
IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18  0
+#define IOMUXC_GPR2_DATA_WIDTH_24  1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET  5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK(1 << 
IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT   (IOMUXC_GPR2_DATA_WIDTH_18 << \
+
IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT   (IOMUXC_GPR2_DATA_WIDTH_24 << \
+
IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED  0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0   1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1   3
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET   0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << 
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
+
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0  (IOMUXC_GPR2_MODE_ENABLED_DI0 
<< \
+
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1  (IOMUXC_GPR2_MODE_ENABLED_DI1 
<< \
+
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
 /* System Reset Controller (SRC) */
 struct src {
u32 scr;
-- 
2.1.4

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[U-Boot] [PATCH v5 4/8] arm: mx5: Add more register definitions

2017-11-06 Thread Martyn Welch 
Add register definitions require for video configuration.

Signed-off-by: Nandor Han 
Signed-off-by: Martyn Welch 
Reviewed-by: Stefano Babic 
Cc: Stefano Babic 
---
Changes in v5:
  - Reduced checkpatch warnings.

 arch/arm/include/asm/arch-mx5/crm_regs.h |  8 
 arch/arm/include/asm/arch-mx5/imx-regs.h | 33 
 2 files changed, 41 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h 
b/arch/arm/include/asm/arch-mx5/crm_regs.h
index b61c7b9..7fea569 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -210,6 +210,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL(0x1 << 1)
 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL0x1
 
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET  26
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK(0x7 << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v)  (((v) & 0x7) << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r)   (((r) >> 26) & 0x7)
+
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
+
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET25
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK  (0x7 << 25)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 2b0dc1e..61c8d44 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -416,6 +416,39 @@ struct iomuxc {
 };
 #endif
 
+#define IOMUXC_GPR2_BITMAP_SPWG0
+#define IOMUXC_GPR2_BITMAP_JEIDA   1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK   (1 << 
IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA  (IOMUXC_GPR2_BITMAP_JEIDA << \
+
IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG   (IOMUXC_GPR2_BITMAP_SPWG << \
+
IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18  0
+#define IOMUXC_GPR2_DATA_WIDTH_24  1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET  5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK(1 << 
IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT   (IOMUXC_GPR2_DATA_WIDTH_18 << \
+
IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT   (IOMUXC_GPR2_DATA_WIDTH_24 << \
+
IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED  0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0   1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1   3
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET   0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << 
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
+
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0  (IOMUXC_GPR2_MODE_ENABLED_DI0 
<< \
+
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1  (IOMUXC_GPR2_MODE_ENABLED_DI1 
<< \
+
IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
 /* System Reset Controller (SRC) */
 struct src {
u32 scr;
-- 
2.1.4

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