Re: [U-Boot] [PATCH v5 6/7] phy: Add USB PHY driver for the cadence USB3
+ Rafal, Anil, Sanket, Jayshri, Rahul > >We are discussing if Cadence/TI/NXP could use the same USB PHY driver > >(drivers/phy/cadence/phy-cadence-sierra.c), I find I can't get > >Alan Douglas , would you please forward related > >people? The question is like below, thanks. > > > >Alan, we find the suggested value at this driver >(drivers/phy/cadence/phy-cadence-sierra.c) > >is so different with "USB 3.0 PHY User Guide for 28FDSOI" CH 3.1.1 Bring-up >Sequence. > >Does this driver support this 28nm PHY? If it supports, why the initialized >value is so different? > >The UG suggested value can be used at NXP platform. > > > >Peter > > > >> > > > >> > > This is indeed a different driver. IMO it would be better to keep > >> > > the driver closer to its linux version. The reason for that is that > >> > > it is quite new and will be adapted when platforms starts supporting > >> > > it. If we start with something too far from the original, it will hard >> > > to update. > >> > > Already I see that the registers initialized are not all the same as > >> > > in the linux driver and not all the values are the same either, nor > >> > > are the register names > >> > > > >> > > TI's J7 platforms is using this PHY driver for USB3/PCIe support, > >> > > and the linux driver has already seen quite a few modifications to > >> > > get it to work > >> > (https://urldefense.proofpoint.com/v2/url?u=https-3A__eur01.safelinks.protection.outlook.com_-3Furl-3Dhttps-253A-252F- >252Fgit.ti&d=DwIGaQ&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-_haXqY&r=e1OgxfvkL0qo9XO6fX1gscva-w03uSYC1nIyxl89- >rI&m=Ip2RbyxoGLS3zuYNjazxkPFURIUZllrs6iSfUmllZGM&s=MG2JpCkGii7tKv3Sb4ekJ08smJd54TTIC6jmZpOdzY0&e= > . > >> > > com%2Fti-linux-kernel%2Fti-linux-kernel%2Fblobs%2Fhistory%2Fti-linux > >> > > - > >> > > 4.19.y%2Fdrivers%2Fphy%2Fcadence%2Fphy-cadence- > >> > > sierra.c&data=02%7C01%7Csherry.sun%40nxp.com%7C84f9122d7eb64 > >> > > 9820bae08d72b997681%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 > >> > > %7C637025810458595586&sdata=6JpD7VcFudhzXSVP0WaGVEp7Fwrue > >> > > A%2B4V6eeOfif19w%3D&reserved=0) > >> > > Adding support for it on top of this current version will be rather >> > > difficult. > >> > > > >> > > >> > Thanks for your advice. > >> > Actually I am not familiar with this phy driver in linux, so also > >> > +peter, who worked on this USB driver under linux, maybe he can give some > >> suggestions. > >> > > >> > >> Add Alan from Cadence > >> > >> Alan, we find the suggested value at this driver >> (drivers/phy/cadence/phy-cadence- > >> sierra.c) > >> is so different with "USB 3.0 PHY User Guide for 28FDSOI" CH 3.1.1 Bring-up > >> Sequence. > >> Does this driver support this 28nm PHY? If it supports, why the initialized >> value is so > >> different? > >> The UG suggested value can be used at NXP platform. > >> > >> Peter ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 6/7] phy: Add USB PHY driver for the cadence USB3
> > > > This is indeed a different driver. IMO it would be better to keep the > > driver closer to its linux version. The reason for that is that it is > > quite new and will be adapted when platforms starts supporting it. If > > we start with something too far from the original, it will hard to update. > > Already I see that the registers initialized are not all the same as > > in the linux driver and not all the values are the same either, nor > > are the register names > > > > TI's J7 platforms is using this PHY driver for USB3/PCIe support, and > > the linux driver has already seen quite a few modifications to get it > > to work > (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ti. > > com%2Fti-linux-kernel%2Fti-linux-kernel%2Fblobs%2Fhistory%2Fti-linux- > > 4.19.y%2Fdrivers%2Fphy%2Fcadence%2Fphy-cadence- > > sierra.c&data=02%7C01%7Csherry.sun%40nxp.com%7C84f9122d7eb64 > > 9820bae08d72b997681%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 > > %7C637025810458595586&sdata=6JpD7VcFudhzXSVP0WaGVEp7Fwrue > > A%2B4V6eeOfif19w%3D&reserved=0) > > Adding support for it on top of this current version will be rather > > difficult. > > > > Thanks for your advice. > Actually I am not familiar with this phy driver in linux, so also +peter, who > worked on > this USB driver under linux, maybe he can give some suggestions. > Add Alan from Cadence Alan, we find the suggested value at this driver (drivers/phy/cadence/phy-cadence-sierra.c) is so different with "USB 3.0 PHY User Guide for 28FDSOI" CH 3.1.1 Bring-up Sequence. Does this driver support this 28nm PHY? If it supports, why the initialized value is so different? The UG suggested value can be used at NXP platform. Peter ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 6/7] phy: Add USB PHY driver for the cadence USB3
Hi Pawel, We are discussing if Cadence/TI/NXP could use the same USB PHY driver (drivers/phy/cadence/phy-cadence-sierra.c), I find I can't get Alan Douglas , would you please forward related people? The question is like below, thanks. Alan, we find the suggested value at this driver (drivers/phy/cadence/phy-cadence-sierra.c) is so different with "USB 3.0 PHY User Guide for 28FDSOI" CH 3.1.1 Bring-up Sequence. Does this driver support this 28nm PHY? If it supports, why the initialized value is so different? The UG suggested value can be used at NXP platform. Peter > > > > > > This is indeed a different driver. IMO it would be better to keep > > > the driver closer to its linux version. The reason for that is that > > > it is quite new and will be adapted when platforms starts supporting > > > it. If we start with something too far from the original, it will hard to > > > update. > > > Already I see that the registers initialized are not all the same as > > > in the linux driver and not all the values are the same either, nor > > > are the register names > > > > > > TI's J7 platforms is using this PHY driver for USB3/PCIe support, > > > and the linux driver has already seen quite a few modifications to > > > get it to work > > (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ti. > > > com%2Fti-linux-kernel%2Fti-linux-kernel%2Fblobs%2Fhistory%2Fti-linux > > > - > > > 4.19.y%2Fdrivers%2Fphy%2Fcadence%2Fphy-cadence- > > > sierra.c&data=02%7C01%7Csherry.sun%40nxp.com%7C84f9122d7eb64 > > > 9820bae08d72b997681%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 > > > %7C637025810458595586&sdata=6JpD7VcFudhzXSVP0WaGVEp7Fwrue > > > A%2B4V6eeOfif19w%3D&reserved=0) > > > Adding support for it on top of this current version will be rather > > > difficult. > > > > > > > Thanks for your advice. > > Actually I am not familiar with this phy driver in linux, so also > > +peter, who worked on this USB driver under linux, maybe he can give some > suggestions. > > > > Add Alan from Cadence > > Alan, we find the suggested value at this driver > (drivers/phy/cadence/phy-cadence- > sierra.c) > is so different with "USB 3.0 PHY User Guide for 28FDSOI" CH 3.1.1 Bring-up > Sequence. > Does this driver support this 28nm PHY? If it supports, why the initialized > value is so > different? > The UG suggested value can be used at NXP platform. > > Peter ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 6/7] phy: Add USB PHY driver for the cadence USB3
Hi Jean, > > +Kishon who worked on this PHY under linux > > > Hi Sherry, > > > On 28/08/2019 10:05, Sherry Sun wrote: > > Hi Jean, > > > >> Hi Sherry, > >> > >> On 21/08/2019 16:36, Sherry Sun wrote: > >>> The cdns3-usb-phy driver supports both host and peripheral mode of > >>> usb driver which use cadence usb3 IP. > >>> > >>> Signed-off-by: Sherry Sun > >>> --- > >>>drivers/phy/Kconfig | 8 ++ > >>>drivers/phy/Makefile| 1 + > >>>drivers/phy/cdns3-usb-phy.c | 241 > >> > >>>3 files changed, 250 insertions(+) > >>>create mode 100644 drivers/phy/cdns3-usb-phy.c > >>> > >>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index > >>> 3942f035eb..1837b32c31 100644 > >>> --- a/drivers/phy/Kconfig > >>> +++ b/drivers/phy/Kconfig > >>> @@ -205,4 +205,12 @@ config MT76X8_USB_PHY > >>> > >>> This PHY is found on MT76x8 devices supporting USB. > >>> > >>> +config CDNS3_USB_PHY > >>> + bool "Support CDNS3 USB PHY" > >>> + depends on PHY > >>> + help > >>> + Support for the USB PHY in CDNS3 IP. > >>> + > >>> + This PHY is found on CDNS3 IP devices supporting USB. > >>> + > >>>endmenu > >>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index > >>> 3157f1b7ee..0e062214d3 100644 > >>> --- a/drivers/phy/Makefile > >>> +++ b/drivers/phy/Makefile > >>> @@ -22,4 +22,5 @@ obj-$(CONFIG_MSM8916_USB_PHY) += msm8916- > >> usbh-phy.o > >>>obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o > >>>obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o > >>>obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o > >>> +obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o > >>>obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o diff --git > >>> a/drivers/phy/cdns3-usb-phy.c b/drivers/phy/cdns3-usb-phy.c new file > >>> mode 100644 index 00..c0d308075b > >>> --- /dev/null > >>> +++ b/drivers/phy/cdns3-usb-phy.c > >>> @@ -0,0 +1,241 @@ > >>> +// SPDX-License-Identifier: GPL-2.0+ > >>> +/* > >>> + * Copyright 2019 NXP > >>> + * > >>> + * Cadence3 USB PHY driver > >>> + * > >>> + * Author: Sherry Sun */ > >>> + > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> + > >>> +/* PHY registers */ > >>> +#define PHY_PMA_CMN_CTRL1(0xC800 * 4) > >>> +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4) > >>> +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4) > >>> +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4) > >>> +#define TB_ADDR_CMN_PLL0_INTDIV (0x0094 * 4) > >>> +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4) > >>> +#define TB_ADDR_CMN_PLL0_HIGH_THR(0x0096 * 4) > >>> +#define TB_ADDR_CMN_PLL0_SS_CTRL1(0x0098 * 4) > >>> +#define TB_ADDR_CMN_PLL0_SS_CTRL2(0x0099 * 4) > >>> +#define TB_ADDR_CMN_PLL0_DSM_DIAG(0x0097 * 4) > >>> +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4) > >>> +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4) > >>> +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4) > >>> +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4) > >>> +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4) > >>> +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4) > >>> +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE (0x01c4 * 4) > >>> +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4) > >>> +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR(0x40ea * 4) > >>> +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4) > >>> +#define TB_ADDR_TX_PSC_A0(0x4100 * 4) > >>> +#define TB_ADDR_TX_PSC_A1(0x4101 * 4) > >>> +#define TB_ADDR_TX_PSC_A2(0x4102 * 4) > >>> +#define TB_ADDR_TX_PSC_A3(0x4103 * 4) > >>> +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4) > >>> +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4) > >>> +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4) > >>> +#define TB_ADDR_RX_PSC_A0(0x8000 * 4) > >>> +#define TB_ADDR_RX_PSC_A1(0x8001 * 4) > >>> +#define TB_ADDR_RX_PSC_A2(0x8002 * 4) > >>> +#define TB_ADDR_RX_PSC_A3(0x8003 * 4) > >>> +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4) > >>> +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4) > >>> +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4) > >>> +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4) > >>> +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4) > >>> +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR(0x8090 * 4) > >>> +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4) > >>> +#define TB_ADDR_RX_DIAG_SIGDET_TUNE (0x81dc * 4) > >>> +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2(0x81df * 4) > >>> +#define TB_ADDR_RX_DIAG
Re: [U-Boot] [PATCH v5 6/7] phy: Add USB PHY driver for the cadence USB3
+Kishon who worked on this PHY under linux Hi Sherry, On 28/08/2019 10:05, Sherry Sun wrote: Hi Jean, Hi Sherry, On 21/08/2019 16:36, Sherry Sun wrote: The cdns3-usb-phy driver supports both host and peripheral mode of usb driver which use cadence usb3 IP. Signed-off-by: Sherry Sun --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile| 1 + drivers/phy/cdns3-usb-phy.c | 241 3 files changed, 250 insertions(+) create mode 100644 drivers/phy/cdns3-usb-phy.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3942f035eb..1837b32c31 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -205,4 +205,12 @@ config MT76X8_USB_PHY This PHY is found on MT76x8 devices supporting USB. +config CDNS3_USB_PHY + bool "Support CDNS3 USB PHY" + depends on PHY + help + Support for the USB PHY in CDNS3 IP. + + This PHY is found on CDNS3 IP devices supporting USB. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3157f1b7ee..0e062214d3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -22,4 +22,5 @@ obj-$(CONFIG_MSM8916_USB_PHY) += msm8916- usbh-phy.o obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o +obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o diff --git a/drivers/phy/cdns3-usb-phy.c b/drivers/phy/cdns3-usb-phy.c new file mode 100644 index 00..c0d308075b --- /dev/null +++ b/drivers/phy/cdns3-usb-phy.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Cadence3 USB PHY driver + * + * Author: Sherry Sun */ + +#include +#include +#include +#include +#include + +/* PHY registers */ +#define PHY_PMA_CMN_CTRL1 (0xC800 * 4) +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4) +#define TB_ADDR_CMN_PLL0_INTDIV(0x0094 * 4) +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4) +#define TB_ADDR_CMN_PLL0_HIGH_THR (0x0096 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (0x0098 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (0x0099 * 4) +#define TB_ADDR_CMN_PLL0_DSM_DIAG (0x0097 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE(0x01c4 * 4) +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4) +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (0x40ea * 4) +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4) +#define TB_ADDR_TX_PSC_A0 (0x4100 * 4) +#define TB_ADDR_TX_PSC_A1 (0x4101 * 4) +#define TB_ADDR_TX_PSC_A2 (0x4102 * 4) +#define TB_ADDR_TX_PSC_A3 (0x4103 * 4) +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4) +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4) +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4) +#define TB_ADDR_RX_PSC_A0 (0x8000 * 4) +#define TB_ADDR_RX_PSC_A1 (0x8001 * 4) +#define TB_ADDR_RX_PSC_A2 (0x8002 * 4) +#define TB_ADDR_RX_PSC_A3 (0x8003 * 4) +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4) +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4) +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4) +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4) +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4) +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (0x8090 * 4) +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4) +#define TB_ADDR_RX_DIAG_SIGDET_TUNE(0x81dc * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (0x81df * 4) +#define TB_ADDR_RX_DIAG_BS_TM (0x81f5 * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (0x81d3 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (0x81c7 * 4) +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0(0x81c2 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (0x81c1 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (0x81c9 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM3 (0x81f8 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM4 (0x81f9 * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE (0x81dd * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL3 (0x81d5 * 4) +#define TB_ADDR_RX_DIAG_SC2C_DELAY
Re: [U-Boot] [PATCH v5 6/7] phy: Add USB PHY driver for the cadence USB3
Hi Jean, > > Hi Sherry, > > On 21/08/2019 16:36, Sherry Sun wrote: > > The cdns3-usb-phy driver supports both host and peripheral mode of usb > > driver which use cadence usb3 IP. > > > > Signed-off-by: Sherry Sun > > --- > > drivers/phy/Kconfig | 8 ++ > > drivers/phy/Makefile| 1 + > > drivers/phy/cdns3-usb-phy.c | 241 > > > 3 files changed, 250 insertions(+) > > create mode 100644 drivers/phy/cdns3-usb-phy.c > > > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index > > 3942f035eb..1837b32c31 100644 > > --- a/drivers/phy/Kconfig > > +++ b/drivers/phy/Kconfig > > @@ -205,4 +205,12 @@ config MT76X8_USB_PHY > > > > This PHY is found on MT76x8 devices supporting USB. > > > > +config CDNS3_USB_PHY > > + bool "Support CDNS3 USB PHY" > > + depends on PHY > > + help > > + Support for the USB PHY in CDNS3 IP. > > + > > + This PHY is found on CDNS3 IP devices supporting USB. > > + > > endmenu > > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index > > 3157f1b7ee..0e062214d3 100644 > > --- a/drivers/phy/Makefile > > +++ b/drivers/phy/Makefile > > @@ -22,4 +22,5 @@ obj-$(CONFIG_MSM8916_USB_PHY) += msm8916- > usbh-phy.o > > obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o > > obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o > > obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o > > +obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o > > obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o diff --git > > a/drivers/phy/cdns3-usb-phy.c b/drivers/phy/cdns3-usb-phy.c new file > > mode 100644 index 00..c0d308075b > > --- /dev/null > > +++ b/drivers/phy/cdns3-usb-phy.c > > @@ -0,0 +1,241 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 NXP > > + * > > + * Cadence3 USB PHY driver > > + * > > + * Author: Sherry Sun */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* PHY registers */ > > +#define PHY_PMA_CMN_CTRL1 (0xC800 * 4) > > +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4) > > +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4) > > +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4) > > +#define TB_ADDR_CMN_PLL0_INTDIV(0x0094 * 4) > > +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4) > > +#define TB_ADDR_CMN_PLL0_HIGH_THR (0x0096 * 4) > > +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (0x0098 * 4) > > +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (0x0099 * 4) > > +#define TB_ADDR_CMN_PLL0_DSM_DIAG (0x0097 * 4) > > +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4) > > +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4) > > +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4) > > +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4) > > +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4) > > +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4) > > +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE(0x01c4 * 4) > > +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4) > > +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (0x40ea * 4) > > +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4) > > +#define TB_ADDR_TX_PSC_A0 (0x4100 * 4) > > +#define TB_ADDR_TX_PSC_A1 (0x4101 * 4) > > +#define TB_ADDR_TX_PSC_A2 (0x4102 * 4) > > +#define TB_ADDR_TX_PSC_A3 (0x4103 * 4) > > +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4) > > +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4) > > +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4) > > +#define TB_ADDR_RX_PSC_A0 (0x8000 * 4) > > +#define TB_ADDR_RX_PSC_A1 (0x8001 * 4) > > +#define TB_ADDR_RX_PSC_A2 (0x8002 * 4) > > +#define TB_ADDR_RX_PSC_A3 (0x8003 * 4) > > +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4) > > +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4) > > +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4) > > +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4) > > +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4) > > +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (0x8090 * 4) > > +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4) > > +#define TB_ADDR_RX_DIAG_SIGDET_TUNE(0x81dc * 4) > > +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (0x81df * 4) > > +#define TB_ADDR_RX_DIAG_BS_TM (0x81f5 * 4) > > +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (0x81d3 * 4) > > +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (0x81c7 * 4) > > +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0(0x81c2 * 4) > > +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (0x81c1 * 4) > > +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (0x81c9 * 4) > > +#define TB_ADDR_RX_DIAG_RXFE_TM3 (0x81f8 * 4) > > +#def
Re: [U-Boot] [PATCH v5 6/7] phy: Add USB PHY driver for the cadence USB3
Hi Sherry, On 21/08/2019 16:36, Sherry Sun wrote: The cdns3-usb-phy driver supports both host and peripheral mode of usb driver which use cadence usb3 IP. Signed-off-by: Sherry Sun --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile| 1 + drivers/phy/cdns3-usb-phy.c | 241 3 files changed, 250 insertions(+) create mode 100644 drivers/phy/cdns3-usb-phy.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3942f035eb..1837b32c31 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -205,4 +205,12 @@ config MT76X8_USB_PHY This PHY is found on MT76x8 devices supporting USB. +config CDNS3_USB_PHY + bool "Support CDNS3 USB PHY" + depends on PHY + help + Support for the USB PHY in CDNS3 IP. + + This PHY is found on CDNS3 IP devices supporting USB. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3157f1b7ee..0e062214d3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -22,4 +22,5 @@ obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o +obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o diff --git a/drivers/phy/cdns3-usb-phy.c b/drivers/phy/cdns3-usb-phy.c new file mode 100644 index 00..c0d308075b --- /dev/null +++ b/drivers/phy/cdns3-usb-phy.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Cadence3 USB PHY driver + * + * Author: Sherry Sun + */ + +#include +#include +#include +#include +#include + +/* PHY registers */ +#define PHY_PMA_CMN_CTRL1 (0xC800 * 4) +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4) +#define TB_ADDR_CMN_PLL0_INTDIV(0x0094 * 4) +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4) +#define TB_ADDR_CMN_PLL0_HIGH_THR (0x0096 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (0x0098 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (0x0099 * 4) +#define TB_ADDR_CMN_PLL0_DSM_DIAG (0x0097 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE(0x01c4 * 4) +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4) +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (0x40ea * 4) +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4) +#define TB_ADDR_TX_PSC_A0 (0x4100 * 4) +#define TB_ADDR_TX_PSC_A1 (0x4101 * 4) +#define TB_ADDR_TX_PSC_A2 (0x4102 * 4) +#define TB_ADDR_TX_PSC_A3 (0x4103 * 4) +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4) +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4) +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4) +#define TB_ADDR_RX_PSC_A0 (0x8000 * 4) +#define TB_ADDR_RX_PSC_A1 (0x8001 * 4) +#define TB_ADDR_RX_PSC_A2 (0x8002 * 4) +#define TB_ADDR_RX_PSC_A3 (0x8003 * 4) +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4) +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4) +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4) +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4) +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4) +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (0x8090 * 4) +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4) +#define TB_ADDR_RX_DIAG_SIGDET_TUNE(0x81dc * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (0x81df * 4) +#define TB_ADDR_RX_DIAG_BS_TM (0x81f5 * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (0x81d3 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (0x81c7 * 4) +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0(0x81c2 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (0x81c1 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (0x81c9 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM3 (0x81f8 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM4 (0x81f9 * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE (0x81dd * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL3 (0x81d5 * 4) +#define TB_ADDR_RX_DIAG_SC2C_DELAY (0x81e1 * 4) +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE (0x81bf * 4) +#define TB_ADDR_XCVR_PSM_CAL_TMR
[U-Boot] [PATCH v5 6/7] phy: Add USB PHY driver for the cadence USB3
The cdns3-usb-phy driver supports both host and peripheral mode of usb driver which use cadence usb3 IP. Signed-off-by: Sherry Sun --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile| 1 + drivers/phy/cdns3-usb-phy.c | 241 3 files changed, 250 insertions(+) create mode 100644 drivers/phy/cdns3-usb-phy.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3942f035eb..1837b32c31 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -205,4 +205,12 @@ config MT76X8_USB_PHY This PHY is found on MT76x8 devices supporting USB. +config CDNS3_USB_PHY + bool "Support CDNS3 USB PHY" + depends on PHY + help + Support for the USB PHY in CDNS3 IP. + + This PHY is found on CDNS3 IP devices supporting USB. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3157f1b7ee..0e062214d3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -22,4 +22,5 @@ obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o +obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o diff --git a/drivers/phy/cdns3-usb-phy.c b/drivers/phy/cdns3-usb-phy.c new file mode 100644 index 00..c0d308075b --- /dev/null +++ b/drivers/phy/cdns3-usb-phy.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Cadence3 USB PHY driver + * + * Author: Sherry Sun + */ + +#include +#include +#include +#include +#include + +/* PHY registers */ +#define PHY_PMA_CMN_CTRL1 (0xC800 * 4) +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4) +#define TB_ADDR_CMN_PLL0_INTDIV(0x0094 * 4) +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4) +#define TB_ADDR_CMN_PLL0_HIGH_THR (0x0096 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (0x0098 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (0x0099 * 4) +#define TB_ADDR_CMN_PLL0_DSM_DIAG (0x0097 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE(0x01c4 * 4) +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4) +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (0x40ea * 4) +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4) +#define TB_ADDR_TX_PSC_A0 (0x4100 * 4) +#define TB_ADDR_TX_PSC_A1 (0x4101 * 4) +#define TB_ADDR_TX_PSC_A2 (0x4102 * 4) +#define TB_ADDR_TX_PSC_A3 (0x4103 * 4) +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4) +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4) +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4) +#define TB_ADDR_RX_PSC_A0 (0x8000 * 4) +#define TB_ADDR_RX_PSC_A1 (0x8001 * 4) +#define TB_ADDR_RX_PSC_A2 (0x8002 * 4) +#define TB_ADDR_RX_PSC_A3 (0x8003 * 4) +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4) +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4) +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4) +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4) +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4) +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (0x8090 * 4) +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4) +#define TB_ADDR_RX_DIAG_SIGDET_TUNE(0x81dc * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (0x81df * 4) +#define TB_ADDR_RX_DIAG_BS_TM (0x81f5 * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (0x81d3 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (0x81c7 * 4) +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0(0x81c2 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (0x81c1 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (0x81c9 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM3 (0x81f8 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM4 (0x81f9 * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE (0x81dd * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL3 (0x81d5 * 4) +#define TB_ADDR_RX_DIAG_SC2C_DELAY (0x81e1 * 4) +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE (0x81bf * 4) +#define TB_ADDR_XCVR_PSM_CAL_TMR (0x4002 * 4) +#define TB_ADDR_XCVR_PSM_A0BYP_TMR
