At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass
Signed-off-by: Bin Meng
Reviewed-by: Bin Meng
---
Changes in v5:
- Squash in Bin's fix-up patch
Changes in v4:
- Add BIOS_CTRL address for PCH9
Changes in v3:
- Use the set_spi_protect() PCH method
Changes in v2:
- Adjust code for earlier commits
- Move the SPI base code into the PCH drivers
arch/x86/cpu/coreboot/pci.c | 3 +-
arch/x86/cpu/irq.c | 7 +-
arch/x86/cpu/ivybridge/bd82x6x.c| 47 ++-
arch/x86/dts/bayleybay.dts | 160 +++-
arch/x86/dts/broadwell_som-6896.dts | 24 --
arch/x86/dts/chromebook_link.dts| 5 +-
arch/x86/dts/chromebox_panther.dts | 34
arch/x86/dts/crownbay.dts | 150 +
arch/x86/dts/galileo.dts| 99 +++---
arch/x86/dts/minnowmax.dts | 158 ++-
arch/x86/dts/qemu-x86_i440fx.dts| 26 +++---
arch/x86/dts/qemu-x86_q35.dts | 38 +
drivers/spi/ich.c | 152 --
13 files changed, 461 insertions(+), 442 deletions(-)
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 41e29a6..7f5087a 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -14,7 +14,8 @@
#include
static const struct udevice_id generic_pch_ids[] = {
- { .compatible = "intel,pch" },
+ { .compatible = "intel,pch7" },
+ { .compatible = "intel,pch9" },
{ }
};
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 35b29f6..205405b 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -97,6 +97,7 @@ static int create_pirq_routing_table(void)
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
+ int parent;
int i;
int ret;
@@ -106,7 +107,11 @@ static int create_pirq_routing_table(void)
return -EINVAL;
}
- ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
+ /* TODO(s...@chromium.org): Drop this when PIRQ is a driver */
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0)
+ return -EINVAL;
+ ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
"reg", &addr);
if (ret)
return ret;
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 434dfd6..c000aca 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -3,12 +3,12 @@
*
* SPDX-License-Identifier:GPL-2.0+
*/
-
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -16,6 +16,8 @@
#include
#include
+#define BIOS_CTRL 0xdc
+
void bd82x6x_pci_init(pci_dev_t dev)
{
u16 reg16;
@@ -96,6 +98,7 @@ static int bd82x6x_probe(struct udevice *dev)
return 0;
}
+/* TODO(s...@chromium.org): Move this to the PCH init() method */
int bd82x6x_init(void)
{
const void *blob = gd->fdt_blob;
@@ -116,6 +119,47 @@ int bd82x6x_init(void)
return 0;
}
+static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+ u32 rcba;
+
+ dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+ /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+ rcba = rcba & 0xc000;
+ *sbasep = rcba + 0x3800;
+
+ return 0;
+}
+
+static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
+{
+ return PCHV_9;
+}
+
+static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
+{
+ uint8_t bios_cntl;
+
+ /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+ dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
+ if (protect) {
+ bios_cntl &= ~BIOS_CTRL_BIOSWE;
+ bios_cntl |= BIT(5);
+ } else {
+ bios_cntl |= BIOS_CTRL_BIOSWE;
+ bios_cntl &= ~BIT(5);
+ }
+ dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+ return 0;
+}
+
+static const struct pch_ops bd82x6x_pch_ops = {
+ .get_sbase = bd82x6x_pch_get_sbase,
+ .get_version= bd82x6x_pch_get_version,
+ .set_sp
