[U-Boot] [PATCH v6] spi: add TI QSPI driver
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v6:
- Added ti related comments
- Created ti spec func for ti code
- Fixed few checkpatch.pl errors
- Rearranged the code.
v4-v5:
- use tabs wherever required.
- remove stray character in license line
- remove get_spi_bus api
- move device control stuff to spi_claim_bus
- Put prints according to the reference driver from jagan
- Move macros below header.files.
drivers/spi/Makefile | 1 +
drivers/spi/ti_qspi.c | 313 ++
2 files changed, 314 insertions(+)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..91a37aa
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,313 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/omap.h
+#include malloc.h
+#include spi.h
+
+/* ti qpsi register bit masks */
+#define QSPI_TIMEOUT200
+#define QSPI_FCLK 19200
+/* clock control */
+#define QSPI_CLK_EN (1 31)
+#define QSPI_CLK_DIV_MAX0x
+/* command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n)((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL(1 16)
+#define QSPI_WR_SNGL(2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD(7 16)
+/* device control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+/* status */
+#define QSPI_WC (1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY(QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT 0xf0ff
+#define MMAP_START_ADDR 0x5c00
+#define CORE_CTRL_IO0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES (0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL (0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS (0x0 24)
+
+/* ti qspi register set */
+struct ti_qspi_regs {
+ u32 pid;
+ u32 pad0[3];
+ u32 sysconfig;
+ u32 pad1[3];
+ u32 intr_status_raw_set;
+ u32 intr_status_enabled_clear;
+ u32 intr_enable_set;
+ u32 intr_enable_clear;
+ u32 intc_eoi;
+ u32 pad2[3];
+ u32 spi_clock_cntrl;
+ u32 spi_dc;
+ u32 spi_cmd;
+ u32 spi_status;
+ u32 spi_data;
+ u32 spi_setup0;
+ u32 spi_setup1;
+ u32 spi_setup2;
+ u32 spi_setup3;
+ u32 spi_switch;
+ u32 spi_data1;
+ u32 spi_data2;
+ u32 spi_data3;
+};
+
+/* ti qspi slave */
+struct ti_qspi_slave {
+ struct spi_slave slave;
+ struct ti_qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_slave, slave);
+}
+
+#ifdef CONFIG_TI_SPI_MMAP
+static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+{
+ struct spi_slave *slave = qslave-slave;
+ u32 memval = 0;
+
+ slave-memory_map = (void *)MMAP_START_ADDR;
+
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
+
Re: [U-Boot] [PATCH v6] spi: add TI QSPI driver
On Monday 07 October 2013 12:33 PM, Jagannadha Sutradharudu Teki wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
Changes for v6:
- Added ti related comments
- Created ti spec func for ti code
- Fixed few checkpatch.pl errors
- Rearranged the code.
v4-v5:
- use tabs wherever required.
- remove stray character in license line
- remove get_spi_bus api
- move device control stuff to spi_claim_bus
- Put prints according to the reference driver from jagan
- Move macros below header.files.
drivers/spi/Makefile | 1 +
drivers/spi/ti_qspi.c | 313 ++
2 files changed, 314 insertions(+)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..91a37aa
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,313 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/arch/omap.h
+#includemalloc.h
+#includespi.h
+
+/* ti qpsi register bit masks */
+#define QSPI_TIMEOUT200
+#define QSPI_FCLK 19200
+/* clock control */
+#define QSPI_CLK_EN (1 31)
+#define QSPI_CLK_DIV_MAX0x
+/* command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n)((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL(1 16)
+#define QSPI_WR_SNGL(2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD(7 16)
+/* device control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+/* status */
+#define QSPI_WC (1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY(QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT 0xf0ff
+#define MMAP_START_ADDR 0x5c00
+#define CORE_CTRL_IO0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES (0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL (0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS (0x0 24)
+
+/* ti qspi register set */
+struct ti_qspi_regs {
+ u32 pid;
+ u32 pad0[3];
+ u32 sysconfig;
+ u32 pad1[3];
+ u32 intr_status_raw_set;
+ u32 intr_status_enabled_clear;
+ u32 intr_enable_set;
+ u32 intr_enable_clear;
+ u32 intc_eoi;
+ u32 pad2[3];
+ u32 spi_clock_cntrl;
+ u32 spi_dc;
+ u32 spi_cmd;
+ u32 spi_status;
+ u32 spi_data;
+ u32 spi_setup0;
+ u32 spi_setup1;
+ u32 spi_setup2;
+ u32 spi_setup3;
+ u32 spi_switch;
+ u32 spi_data1;
+ u32 spi_data2;
+ u32 spi_data3;
+};
+
+/* ti qspi slave */
+struct ti_qspi_slave {
+ struct spi_slave slave;
+ struct ti_qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_slave, slave);
+}
+
+#ifdef CONFIG_TI_SPI_MMAP
+static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+{
+ struct spi_slave *slave =qslave-slave;
+ u32 memval = 0;
+
+ slave-memory_map = (void *)MMAP_START_ADDR;
+
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+
