Re: [U-Boot] [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock driver
On Mon, 2019-02-11 at 04:32 +, Anup Patel wrote: > > -Original Message- > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de] > > Sent: Monday, February 11, 2019 12:10 AM > > To: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com; > > joe.hershber...@ni.com; r...@andestech.com; > > yamada.masah...@socionext.com; mon...@monstr.eu; Anup Patel > > > > Cc: paul.walms...@sifive.com; pal...@sifive.com; > > u-boot@lists.denx.de; > > ag...@suse.de; Atish Patra > > Subject: Re: [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock > > driver > > > > On Sat, 2019-02-09 at 06:32 +, Anup Patel wrote: > > > Add driver code for the SiFive FU540 PRCI IP block. This IP > > > block > > > handles reset and clock control for the SiFive FU540 device and > > > implements SoC-level clock tree controls and dividers. > > > > > > Based on code written by Wesley Terpstra > > > found in > > > commit 999529edf517ed75b56659d456d221b2ee56bb60 of: > > > https://github.com/riscv/riscv-linux > > > > > > Boot and PLL rate change were tested on a SiFive HiFive Unleashed > > > board. > > > > > > Signed-off-by: Paul Walmsley > > > Signed-off-by: Atish Patra > > > Signed-off-by: Anup Patel > > > Reviewed-by: Alexander Graf > > > --- > > > drivers/clk/Kconfig | 1 + > > > drivers/clk/Makefile | 1 + > > > drivers/clk/sifive/Kconfig| 19 + > > > drivers/clk/sifive/Makefile | 5 + > > > .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++ > > > drivers/clk/sifive/fu540-prci.c | 604 > > > ++ > > > drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++ > > > include/dt-bindings/clk/sifive-fu540-prci.h | 29 + > > > 8 files changed, 1150 insertions(+) > > > create mode 100644 drivers/clk/sifive/Kconfig create mode > > > 100644 > > > drivers/clk/sifive/Makefile create mode 100644 > > > drivers/clk/sifive/analogbits-wrpll-cln28hpc.h > > > create mode 100644 drivers/clk/sifive/fu540-prci.c create mode > > > 100644 drivers/clk/sifive/wrpll-cln28hpc.c > > > create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h > > > > > > > This patch currently does not apply cleanly on U-Boot master. > > The patches are based upon latest RISC-V U-Boot tree > (git://git.denx.de/u-boot-riscv.git) at commit id > 91882c472d8c0aef4db699d3f2de55bf43d4ae4b > > Do you want me to base this upon U-Boot master ?? > > Regards, > Anup Yes, that's what I meant. The series applies cleanly now, thanks! Lukas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock driver
> -Original Message- > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de] > Sent: Monday, February 11, 2019 12:10 AM > To: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com; > joe.hershber...@ni.com; r...@andestech.com; > yamada.masah...@socionext.com; mon...@monstr.eu; Anup Patel > > Cc: paul.walms...@sifive.com; pal...@sifive.com; u-boot@lists.denx.de; > ag...@suse.de; Atish Patra > Subject: Re: [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock driver > > On Sat, 2019-02-09 at 06:32 +, Anup Patel wrote: > > Add driver code for the SiFive FU540 PRCI IP block. This IP block > > handles reset and clock control for the SiFive FU540 device and > > implements SoC-level clock tree controls and dividers. > > > > Based on code written by Wesley Terpstra found in > > commit 999529edf517ed75b56659d456d221b2ee56bb60 of: > > https://github.com/riscv/riscv-linux > > > > Boot and PLL rate change were tested on a SiFive HiFive Unleashed > > board. > > > > Signed-off-by: Paul Walmsley > > Signed-off-by: Atish Patra > > Signed-off-by: Anup Patel > > Reviewed-by: Alexander Graf > > --- > > drivers/clk/Kconfig | 1 + > > drivers/clk/Makefile | 1 + > > drivers/clk/sifive/Kconfig| 19 + > > drivers/clk/sifive/Makefile | 5 + > > .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++ > > drivers/clk/sifive/fu540-prci.c | 604 > > ++ > > drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++ > > include/dt-bindings/clk/sifive-fu540-prci.h | 29 + > > 8 files changed, 1150 insertions(+) > > create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 > > drivers/clk/sifive/Makefile create mode 100644 > > drivers/clk/sifive/analogbits-wrpll-cln28hpc.h > > create mode 100644 drivers/clk/sifive/fu540-prci.c create mode > > 100644 drivers/clk/sifive/wrpll-cln28hpc.c > > create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h > > > > This patch currently does not apply cleanly on U-Boot master. The patches are based upon latest RISC-V U-Boot tree (git://git.denx.de/u-boot-riscv.git) at commit id 91882c472d8c0aef4db699d3f2de55bf43d4ae4b Do you want me to base this upon U-Boot master ?? Regards, Anup ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock driver
On Sat, 2019-02-09 at 06:32 +, Anup Patel wrote: > Add driver code for the SiFive FU540 PRCI IP block. This IP block > handles reset and clock control for the SiFive FU540 device and > implements SoC-level clock tree controls and dividers. > > Based on code written by Wesley Terpstra > found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: > https://github.com/riscv/riscv-linux > > Boot and PLL rate change were tested on a SiFive HiFive Unleashed > board. > > Signed-off-by: Paul Walmsley > Signed-off-by: Atish Patra > Signed-off-by: Anup Patel > Reviewed-by: Alexander Graf > --- > drivers/clk/Kconfig | 1 + > drivers/clk/Makefile | 1 + > drivers/clk/sifive/Kconfig| 19 + > drivers/clk/sifive/Makefile | 5 + > .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++ > drivers/clk/sifive/fu540-prci.c | 604 > ++ > drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++ > include/dt-bindings/clk/sifive-fu540-prci.h | 29 + > 8 files changed, 1150 insertions(+) > create mode 100644 drivers/clk/sifive/Kconfig > create mode 100644 drivers/clk/sifive/Makefile > create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h > create mode 100644 drivers/clk/sifive/fu540-prci.c > create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c > create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h > This patch currently does not apply cleanly on U-Boot master. Thanks, Lukas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock driver
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sifive/Kconfig| 19 + drivers/clk/sifive/Makefile | 5 + .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++ drivers/clk/sifive/fu540-prci.c | 604 ++ drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++ include/dt-bindings/clk/sifive-fu540-prci.h | 29 + 8 files changed, 1150 insertions(+) create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 drivers/clk/sifive/Makefile create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h create mode 100644 drivers/clk/sifive/fu540-prci.c create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index eadf7f8250..ce462f5717 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -104,6 +104,7 @@ source "drivers/clk/imx/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/sifive/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 9acbb1a650..2f4446568c 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ +obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig new file mode 100644 index 00..81fc9f8fda --- /dev/null +++ b/drivers/clk/sifive/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 + +config CLK_ANALOGBITS_WRPLL_CLN28HPC + bool + +config CLK_SIFIVE + bool "SiFive SoC driver support" + depends on CLK + help + SoC drivers for SiFive Linux-capable SoCs. + +config CLK_SIFIVE_FU540_PRCI + bool "PRCI driver for SiFive FU540 SoCs" + depends on CLK_SIFIVE + select CLK_ANALOGBITS_WRPLL_CLN28HPC + help + Supports the Power Reset Clock interface (PRCI) IP block found in + FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, + enable this driver. diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile new file mode 100644 index 00..1155e07e37 --- /dev/null +++ b/drivers/clk/sifive/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)+= wrpll-cln28hpc.o + +obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)+= fu540-prci.o diff --git a/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h new file mode 100644 index 00..4432e24749 --- /dev/null +++ b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Copyright (C) 2018 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H +#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H + +#include + +/* DIVQ_VALUES: number of valid DIVQ values */ +#define DIVQ_VALUES6 + +/* + * Bit definitions for struct analogbits_wrpll_cfg.flags + * + * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be + * programmed to enter bypass + * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset + * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal + * feedback mode + * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external + * feedback mode (not yet supported by this driver) + * + * The flags
