this is jz4740 base head file
Signed-off-by: Xiangfu Liu
Acked-by: Daniel
---
Changes for v2:
- remove useless code, prepare for using io.h
- delete all base + offset. using C struct
arch/mips/include/asm/jz4740.h | 1102
1 files changed, 1102 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/include/asm/jz4740.h
diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
new file mode 100644
index 000..e9209f6
--- /dev/null
+++ b/arch/mips/include/asm/jz4740.h
@@ -0,0 +1,1102 @@
+/*
+ * head file for Ingenic Semiconductor's JZ4740 CPU.
+ */
+#ifndef __JZ4740_H__
+#define __JZ4740_H__
+
+#include
+#include
+
+/* Boot ROM Specification */
+/* NOR Boot config */
+#define JZ4740_NORBOOT_8BIT0x /* 8-bit data bus flash */
+#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
+#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
+/* NAND Boot config */
+#define JZ4740_NANDBOOT_B8R3 0x /* 8-bit bus & 3 row cycles */
+#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
+#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
+#define JZ4740_NANDBOOT_B16R2 0x /* 16-bit bus & 2 row cycles */
+
+/* 1st-level interrupts */
+#define JZ4740_IRQ_I2C 1
+#define JZ4740_IRQ_UHC 3
+#define JZ4740_IRQ_UART0 9
+#define JZ4740_IRQ_SADC12
+#define JZ4740_IRQ_MSC 14
+#define JZ4740_IRQ_RTC 15
+#define JZ4740_IRQ_SSI 16
+#define JZ4740_IRQ_CIM 17
+#define JZ4740_IRQ_AIC 18
+#define JZ4740_IRQ_ETH 19
+#define JZ4740_IRQ_DMAC20
+#define JZ4740_IRQ_TCU221
+#define JZ4740_IRQ_TCU122
+#define JZ4740_IRQ_TCU023
+#define JZ4740_IRQ_UDC 24
+#define JZ4740_IRQ_GPIO3 25
+#define JZ4740_IRQ_GPIO2 26
+#define JZ4740_IRQ_GPIO1 27
+#define JZ4740_IRQ_GPIO0 28
+#define JZ4740_IRQ_IPU 29
+#define JZ4740_IRQ_LCD 30
+/* 2nd-level interrupts */
+#define JZ4740_IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
+#define JZ4740_IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
+
+/* Register Definitions */
+#defineJZ4740_CPM_BASE 0x1000
+#defineJZ4740_INTC_BASE0x10001000
+#defineJZ4740_TCU_BASE 0x10002000
+#defineJZ4740_WDT_BASE 0x10002000
+#defineJZ4740_RTC_BASE 0x10003000
+#defineJZ4740_GPIO_BASE0x1001
+#defineJZ4740_AIC_BASE 0x1002
+#defineJZ4740_ICDC_BASE0x1002
+#defineJZ4740_MSC_BASE 0x10021000
+#defineJZ4740_UART0_BASE 0x1003
+#defineJZ4740_I2C_BASE 0x10042000
+#defineJZ4740_SSI_BASE 0x10043000
+#defineJZ4740_SADC_BASE0x1007
+#defineJZ4740_EMC_BASE 0x1301
+#defineJZ4740_DMAC_BASE0x1302
+#defineJZ4740_UHC_BASE 0x1303
+#defineJZ4740_UDC_BASE 0x1304
+#defineJZ4740_LCD_BASE 0x1305
+#defineJZ4740_SLCD_BASE0x1305
+#defineJZ4740_CIM_BASE 0x1306
+#defineJZ4740_ETH_BASE 0x1310
+
+/* 8bit Mode Register of SDRAM bank 0 */
+#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000)
+
+/* GPIO (General-Purpose I/O Ports) */
+/* = 0,1,2,3 */
+#define GPIO_PXPIN(n) (JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level
Register */
+#define GPIO_PXDAT(n) (JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data
Register */
+#define GPIO_PXDATS(n) (JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data
Set Register */
+#define GPIO_PXDATC(n) (JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data
Clear Register */
+#define GPIO_PXIM(n) (JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt
Mask Register */
+#define GPIO_PXIMS(n) (JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt
Mask Set Reg */
+#define GPIO_PXIMC(n) (JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt
Mask Clear Reg */
+#define GPIO_PXPE(n) (JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable
Register */
+#define GPIO_PXPES(n) (JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable
Set Reg. */
+#define GPIO_PXPEC(n) (JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable
Clear Reg. */
+#define GPIO_PXFUN(n) (JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function
Register */
+#define GPIO_PXFUNS(n) (JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set
Register */
+#define GPIO_PXFUNC(n) (JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function
Clear Register */
+#define GPIO_PXSEL(n) (JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select
Register */
+#define GPIO_PXSELS(n) (JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set
Register */
+#define GPIO_PXSELC(n) (JZ4740
