Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Hi! Actually socfpga board folder includes code to support both Cyclone V and Arria V soc dev kit. ok. I expect that you are talking about 2 completely different boards which are here http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html http://www.altera.com/products/devkits/altera/kit-arria-v-soc.html Can you use the same configuration on both of them at the same time? I hardly believe that everything just match. Actually, there's third board, called SoCrates, and yes, exactly same configuration works on it and cyclone-v. What about Arria-V? So you better start believing :-). Maybe I will start to believe that Altera design all board the same like position of pins for uarts, spi, ethernet, etc. At least Sockit and Socrates are pretty similar in that regard. Apart from the things that are not ;-) Take for example the DDR3 pins on the FPGA side. The Sockit has DDR3-RAM, the Socrates hasn't. So, the pinsetup is different for both. And when you mess that up in the prebootloader, you can't AFAIK change that later. The boards will boot just fine with the same barebox image, but that doesn't mean, that everything is setup correctly. That is what I meant -- you still have useful box running Linux. Having something useful that boots out of the box is important. And it seems to be same(-enough) between Socrates and Arria, too. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
On 04/03/2014 11:35 AM, Pavel Machek wrote: Hi! Actually socfpga board folder includes code to support both Cyclone V and Arria V soc dev kit. ok. I expect that you are talking about 2 completely different boards which are here http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html http://www.altera.com/products/devkits/altera/kit-arria-v-soc.html Can you use the same configuration on both of them at the same time? I hardly believe that everything just match. Actually, there's third board, called SoCrates, and yes, exactly same configuration works on it and cyclone-v. What about Arria-V? So you better start believing :-). Maybe I will start to believe that Altera design all board the same like position of pins for uarts, spi, ethernet, etc. At least Sockit and Socrates are pretty similar in that regard. Apart from the things that are not ;-) Take for example the DDR3 pins on the FPGA side. The Sockit has DDR3-RAM, the Socrates hasn't. So, the pinsetup is different for both. And when you mess that up in the prebootloader, you can't AFAIK change that later. The boards will boot just fine with the same barebox image, but that doesn't mean, that everything is setup correctly. That is what I meant -- you still have useful box running Linux. Having something useful that boots out of the box is important. And it seems to be same(-enough) between Socrates and Arria, too. It is more about user expectation and explanation it was sent. 1. Here Chin was referring that it is one board http://lists.denx.de/pipermail/u-boot/2014-March/174866.html and here you are saying that it is for all Altera's development boards. It means it is generic board support what I was telling from the start and this configuration just luckily fits to more boards. 2. Altera is likely designing boards in very similar way that use the same console, same DDRs(or working with the same timing), i2c pins, spi pins, whatever. You are just lucky that one configuration is working for more boards but they are not 100% fit. I expect that they use the same oscillator and when someone change it then this default configuration just stop to work. That's why you should at least print any message that this is default or minimum or fail-safe configuration and none should use it in final product because simple it doesn't match what they have setup in design tool. Or just write that this configuration is for this development board and it also working for these development boards. From that WARNING, everybody should be aware that they have to replace that generated files by their custom files which fit their design. Then it is clear that they have something what it boots but they have something what they shouldn't use in final product. 3. Have something useful that boots can be done with less lines than it is done right now. From my experience with Zynq you don't need 600 lines of magic setting to have something useful which boots. 4. It is just question of time when Altera release the board where different uart or oscillator is used and you won't have something useful what boot. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Hi! Actually socfpga board folder includes code to support both Cyclone V and Arria V soc dev kit. ok. I expect that you are talking about 2 completely different boards which are here http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html http://www.altera.com/products/devkits/altera/kit-arria-v-soc.html Can you use the same configuration on both of them at the same time? I hardly believe that everything just match. Actually, there's third board, called SoCrates, and yes, exactly same configuration works on it and cyclone-v. So you better start believing :-). Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Hi Pavel On 04/01/2014 10:46 AM, Pavel Machek wrote: Hi! Actually socfpga board folder includes code to support both Cyclone V and Arria V soc dev kit. ok. I expect that you are talking about 2 completely different boards which are here http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html http://www.altera.com/products/devkits/altera/kit-arria-v-soc.html Can you use the same configuration on both of them at the same time? I hardly believe that everything just match. Actually, there's third board, called SoCrates, and yes, exactly same configuration works on it and cyclone-v. What about Arria-V? So you better start believing :-). Maybe I will start to believe that Altera design all board the same like position of pins for uarts, spi, ethernet, etc. Steffen sent some days ago these two patches to barebox http://www.spinics.net/lists/u-boot-v2/msg18357.html http://www.spinics.net/lists/u-boot-v2/msg18358.html where he is actually the same as I am saying The current iocsr-config-cyclone5.c is actually board specific, although the file name suggests otherwise. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Hi! On Tue, Apr 01, 2014 at 11:07:45AM +0200, Michal Simek wrote: Hi Pavel On 04/01/2014 10:46 AM, Pavel Machek wrote: Hi! Actually socfpga board folder includes code to support both Cyclone V and Arria V soc dev kit. ok. I expect that you are talking about 2 completely different boards which are here http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html http://www.altera.com/products/devkits/altera/kit-arria-v-soc.html Can you use the same configuration on both of them at the same time? I hardly believe that everything just match. Actually, there's third board, called SoCrates, and yes, exactly same configuration works on it and cyclone-v. What about Arria-V? So you better start believing :-). Maybe I will start to believe that Altera design all board the same like position of pins for uarts, spi, ethernet, etc. At least Sockit and Socrates are pretty similar in that regard. Apart from the things that are not ;-) Take for example the DDR3 pins on the FPGA side. The Sockit has DDR3-RAM, the Socrates hasn't. So, the pinsetup is different for both. And when you mess that up in the prebootloader, you can't AFAIK change that later. The boards will boot just fine with the same barebox image, but that doesn't mean, that everything is setup correctly. Steffen sent some days ago these two patches to barebox http://www.spinics.net/lists/u-boot-v2/msg18357.html http://www.spinics.net/lists/u-boot-v2/msg18358.html where he is actually the same as I am saying The current iocsr-config-cyclone5.c is actually board specific, although the file name suggests otherwise. I did this for example, because the Socrates needs the i2c clock pulled up. The Sockit doesn't. Regards, Steffen -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Hi Chin, On 03/24/2014 04:21 PM, Chin Liang See wrote: Hi Michal, On Wed, 2014-03-12 at 15:54 +0100, Michal Simek wrote: On 03/12/2014 03:45 PM, Chin Liang See wrote: Hi guys, Any ACK or further comments? I still have a comment that you should at least rename your socfpga board name to something better because currently it is more suggesting that this is generic socfpga arch support not cyclone V soc dev kit. Actually socfpga board folder includes code to support both Cyclone V and Arria V soc dev kit. ok. I expect that you are talking about 2 completely different boards which are here http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html http://www.altera.com/products/devkits/altera/kit-arria-v-soc.html Can you use the same configuration on both of them at the same time? I hardly believe that everything just match. You mentioned here that it is Altera dev kit (means one board) http://lists.denx.de/pipermail/u-boot/2014-March/174866.html based on your comment above Altera dev kit means two boards with different family and layout. From your responses this is just what I though that board/altera/socfpga is generic socfpga board support not specific socfpga board support which should contain this huge config setting which target just one board. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Hi Michal, On Wed, 2014-03-12 at 15:54 +0100, Michal Simek wrote: On 03/12/2014 03:45 PM, Chin Liang See wrote: Hi guys, Any ACK or further comments? I still have a comment that you should at least rename your socfpga board name to something better because currently it is more suggesting that this is generic socfpga arch support not cyclone V soc dev kit. Actually socfpga board folder includes code to support both Cyclone V and Arria V soc dev kit. Thanks Chin Liang Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Hi Michal,
On Wed, 2014-03-12 at 15:57 +0100, Michal Simek wrote:
On 03/05/2014 05:05 PM, Chin Liang See wrote:
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v7
- Enhance the function scan_chain_engine_is_idle
Changes for v6
- Fixed various coding style issue
Changes for v5
- Removal of additional blank line
- Added comment for magic number
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 980 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
+ /*
+* Program the last part of IO scan chain write TDI_TDO packet
+* header (2 bytes) to scan manager
+*/
+ writel(tdi_tdo_header, scan_manager_base-fifo_double_byte);
+
+ for (i = 0; i io_program_iter; i++) {
+ /*
+* write remaining scan chain data into scan
+* manager WFIFO with 4 bytes write
+ */
Wrong indentation here.
Just a small cosmetic error. I would just leave it as of now.
+ writel(iocsr_scan_chain[index + i],
+ scan_manager_base-fifo_quad_byte);
+ }
+
+ index += io_program_iter;
+ residual = io_scan_chain_data_residual
+ IO_SCAN_CHAIN_32BIT_MASK;
+
+ if (IO_SCAN_CHAIN_PAYLOAD_24BIT residual) {
+ /*
+* write the last 4B scan chain data
+* into scan manager WFIFO
+*/
+ writel(iocsr_scan_chain[index],
+ scan_manager_base-fifo_quad_byte);
+ } else {
+ /*
+* write the remaining 1 - 3 bytes scan chain
+* data into scan manager WFIFO byte by byte
+* to prevent JTAG engine shifting unused data
+* from the FIFO and mistaken the data as a
+* valid command (even though unused bits are
+* set to 0, but just to prevent hardware
+* glitch)
+*/
+ for (i = 0; i residual; i += 8) {
+ writel(((iocsr_scan_chain[index] i)
+IO_SCAN_CHAIN_BYTE_MASK),
+ scan_manager_base-fifo_single_byte);
+ }
+ }
+
+ /*
+* Check if the scan chain engine has completed the
+* IO scan chain data shifting
+*/
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ goto error;
+ }
+
+ /* Disable IO Scan chain when configuration done*/
space*/ here.
same as above.
Thanks
Chin Liang
Thanks,
Michal
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Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Hi guys,
Any ACK or further comments?
Thanks
Chin Liang
On Wed, 2014-03-05 at 10:05 -0600, Chin Liang See wrote:
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v7
- Enhance the function scan_chain_engine_is_idle
Changes for v6
- Fixed various coding style issue
Changes for v5
- Removal of additional blank line
- Added comment for magic number
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 980 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index cbe1d40..eb33f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y:= lowlevel_init.o
obj-y+= misc.o timer.o reset_manager.o system_manager.o
clock_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..a820b1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/freeze_controller.h
+#include asm/arch/scan_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(scan_manager_base-stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+ (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) 0)) {
+ max_iter--;
+ if (max_iter 0)
+ scanmgr_status = readl(scan_manager_base-stat);
+ else
+ return 0;
+ }
+ return 1;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /*
+ * De-assert reinit if the IO scan chain is intended for HIO. In
+ * this, its the chain 3.
+ */
+ if (io_scan_chain_id == 3)
+ clrbits_le32(freeze_controller_base-hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+ * Check if the scan chain engine is inactive and the
+ * WFIFO is empty before enabling the IO scan chain
+ */
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ return 1;
+
+ /*
+ * Enable IO Scan chain based on scan chain id
+ * Note: only one chain can be enabled at a time
+ */
+ setbits_le32(scan_manager_base-en, 1 io_scan_chain_id);
+
+ /*
+ * Calculate number of iteration needed for full 128-bit (4 x32-bits)
+ * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+ */
+ io_program_iter =
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
On 03/12/2014 03:45 PM, Chin Liang See wrote: Hi guys, Any ACK or further comments? I still have a comment that you should at least rename your socfpga board name to something better because currently it is more suggesting that this is generic socfpga arch support not cyclone V soc dev kit. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
On 03/05/2014 05:05 PM, Chin Liang See wrote:
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v7
- Enhance the function scan_chain_engine_is_idle
Changes for v6
- Fixed various coding style issue
Changes for v5
- Removal of additional blank line
- Added comment for magic number
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 980 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index cbe1d40..eb33f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y:= lowlevel_init.o
obj-y+= misc.o timer.o reset_manager.o system_manager.o
clock_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..a820b1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/freeze_controller.h
+#include asm/arch/scan_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(scan_manager_base-stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+ (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) 0)) {
+ max_iter--;
+ if (max_iter 0)
+ scanmgr_status = readl(scan_manager_base-stat);
+ else
+ return 0;
+ }
+ return 1;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /*
+ * De-assert reinit if the IO scan chain is intended for HIO. In
+ * this, its the chain 3.
+ */
+ if (io_scan_chain_id == 3)
+ clrbits_le32(freeze_controller_base-hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+ * Check if the scan chain engine is inactive and the
+ * WFIFO is empty before enabling the IO scan chain
+ */
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ return 1;
+
+ /*
+ * Enable IO Scan chain based on scan chain id
+ * Note: only one chain can be enabled at a time
+ */
+ setbits_le32(scan_manager_base-en, 1 io_scan_chain_id);
+
+ /*
+ * Calculate number of iteration needed for full 128-bit (4 x32-bits)
+ * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+ */
+ io_program_iter = io_scan_chain_len_in_bits
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+
[U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v7
- Enhance the function scan_chain_engine_is_idle
Changes for v6
- Fixed various coding style issue
Changes for v5
- Removal of additional blank line
- Added comment for magic number
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 980 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index cbe1d40..eb33f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..a820b1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/freeze_controller.h
+#include asm/arch/scan_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(scan_manager_base-stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+ (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) 0)) {
+ max_iter--;
+ if (max_iter 0)
+ scanmgr_status = readl(scan_manager_base-stat);
+ else
+ return 0;
+ }
+ return 1;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /*
+* De-assert reinit if the IO scan chain is intended for HIO. In
+* this, its the chain 3.
+*/
+ if (io_scan_chain_id == 3)
+ clrbits_le32(freeze_controller_base-hioctrl,
+SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ return 1;
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(scan_manager_base-en, 1 io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /*
