From: Kuo-Jung Su
Faraday FTNANDC021 is an integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example:
Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation.
Signed-off-by: Kuo-Jung Su
CC: Albert ARIBAUD
CC: Scott Wood
---
Changes for v7:
- ftnandc021.[ch]: Update license to use SPDX identifiers.
- ftnandc021.c: put_unaligned() -> memcpy()
- ftnandc021.c: update ecc relatived function prototypes to
fix compile warnnings.
Changes for v6:
- Update README for CONFIG_SYS_FTNANDC021_TIMING
- Remove illegal type-punning by introducing
put_unaligned() & get_unaligned().
Changes for v5 (Part of A360/A369 patch series):
- Coding Style cleanup:
struct chip_regs __iomem *regs -> struct chip_regs *regs
- For there is a strong dependancy between this and A360/A369 patch
series, it had been chained back to A360/A369 patch series.
- The latest nand_base requires the ecc.strength to be set properlly,
so this patch adds ecc.strength setting accroding to ECC algorithm.
Changes for v5 (Standalone):
- Update README for the description of CONFIG_SYS_FTNANDC021_TIMING.
- Drop redundant white space. (i.e. if (mtd->writesize >= ' '4096))
Changes for v4:
- Make it a separate patch, rather then a part of
Faraday A36x patch series
- Drop the faraday/nand.h to remove dependency to
Faraday A36x patch series.
- CONFIG_SYS_NAND_TIMING -> CONFIG_SYS_FTNANDC021_TIMING
- Remove non-ECC code.
- Implement private hwecc read/write_page functions
to get rid of .eccpos & .eccbytes.
- Use macro constants for timeout control
Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Replace all the infinite wait loop with a timeout.
- Add '__iomem' to all the declaration of HW register pointers.
- Re-write this driver with ECC enabled and correct column address
handling for OOB read/write,
- Fix issuses addressed by Scott.
Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().
README| 10 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/ftnandc021.c | 609 +
include/faraday/ftnandc021.h | 152 ++
4 files changed, 772 insertions(+)
create mode 100644 drivers/mtd/nand/ftnandc021.c
create mode 100644 include/faraday/ftnandc021.h
diff --git a/README b/README
index a5c3e8d..f4b0dbe 100644
--- a/README
+++ b/README
@@ -4076,6 +4076,16 @@ Low Level (hardware related) configuration options:
- drivers/mtd/nand/ndfc.c
- drivers/mtd/nand/mxc_nand.c
+- CONFIG_SYS_FTNANDC021_TIMING
+ This option specifies an array of customized timing parameters
+ for Faraday FTNANDC021 NAND flash controller.
+ e.g.
+ #define CONFIG_SYS_FTNANDC021_TIMING \
+ { CONFIG_NAND_K9F4G08U0B_AC1,
CONFIG_NAND_K9F4G08U0B_AC2 }
+ where CONFIG_NAND_K9F4G08U0B_AC[1/2] are the optimized AC
+ timing parameters for register AC_TIMING1 and AC_TIMING2 which
+ control the timing for CLE, ALE, WE and RE signals.
+
- CONFIG_SYS_NDFC_EBC0_CFG
Sets the EBC0_CFG register for the NDFC. If not defined
a default value will be used.
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index e27e0b7..ee85b8a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -48,6 +48,7 @@ COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o
+COBJS-$(CONFIG_NAND_FTNANDC021) += ftnandc021.o
COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
diff --git a/drivers/mtd/nand/ftnandc021.c b/drivers/mtd/nand/ftnandc021.c
new file mode 100644
index 000..9d249f7
--- /dev/null
+++ b/drivers/mtd/nand/ftnandc021.c
@@ -0,0 +1,609 @@
+/*
+ * Faraday NAND Flash Controller
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
+#define CFG_PIO_TIMEOUT (CONFIG_SYS_HZ >> 3) /* 125 ms */
+
+struct ftnandc021_chip {
+ void __iomem *regs;
+ int alen;
+ int pgsz;
+ int bksz;
+
+ int col;/* current column address */
+ int page; /* current row address/page index */
+ int cmd;
