Signed-off-by: Matthias Ludwig mlud...@ultratronik.de
---
board/omap3/evm/evm.c | 15 +++
cpu/arm_cortexa8/omap3/mem.c | 21 ++---
cpu/arm_cortexa8/omap3/sys_info.c |3 +--
drivers/mtd/nand/omap_gpmc.c | 33 -
4 files changed, 34 insertions(+), 38 deletions(-)
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c
index 7747986..efbb405 100644
--- a/board/omap3/evm/evm.c
+++ b/board/omap3/evm/evm.c
@@ -92,17 +92,16 @@ void set_muxconf_regs(void)
static void setup_net_chip(void)
{
struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
- struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */
- writel(NET_GPMC_CONFIG1, gpmc-cs[5].config1);
- writel(NET_GPMC_CONFIG2, gpmc-cs[5].config2);
- writel(NET_GPMC_CONFIG3, gpmc-cs[5].config3);
- writel(NET_GPMC_CONFIG4, gpmc-cs[5].config4);
- writel(NET_GPMC_CONFIG5, gpmc-cs[5].config5);
- writel(NET_GPMC_CONFIG6, gpmc-cs[5].config6);
- writel(NET_GPMC_CONFIG7, gpmc-cs[5].config7);
+ writel(NET_GPMC_CONFIG1, gpmc_cfg-cs[5].config1);
+ writel(NET_GPMC_CONFIG2, gpmc_cfg-cs[5].config2);
+ writel(NET_GPMC_CONFIG3, gpmc_cfg-cs[5].config3);
+ writel(NET_GPMC_CONFIG4, gpmc_cfg-cs[5].config4);
+ writel(NET_GPMC_CONFIG5, gpmc_cfg-cs[5].config5);
+ writel(NET_GPMC_CONFIG6, gpmc_cfg-cs[5].config6);
+ writel(NET_GPMC_CONFIG7, gpmc_cfg-cs[5].config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(ctrl_base -gpmc_nwe) | 0x0E00, ctrl_base-gpmc_nwe);
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index aa15f94..079c848 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -41,6 +41,8 @@ unsigned int boot_flash_sec;
unsigned int boot_flash_type;
volatile unsigned int boot_flash_env_addr;
+struct gpmc *gpmc_cfg;
+
#if defined(CONFIG_CMD_NAND)
static u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
@@ -51,8 +53,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG6, 0
};
-struct gpmc *gpmc_cfg;
-
#if defined(CONFIG_ENV_IS_IN_NAND)
#define GPMC_CS 0
#else
@@ -219,7 +219,7 @@ void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
u32 *gpmc_config = NULL;
- struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
+ gpmc_cfg = (struct gpmc *)GPMC_BASE;
u32 base = 0;
u32 size = 0;
u32 f_off = CONFIG_SYS_MONITOR_LEN;
@@ -227,27 +227,26 @@ void gpmc_init(void)
u32 config = 0;
/* global settings */
- writel(0, gpmc_base-irqenable); /* isr's sources masked */
- writel(0, gpmc_base-timeout_control);/* timeout disable */
+ writel(0, gpmc_cfg-irqenable); /* isr's sources masked */
+ writel(0, gpmc_cfg-timeout_control);/* timeout disable */
- config = readl(gpmc_base-config);
+ config = readl(gpmc_cfg-config);
config = (~0xf00);
- writel(config, gpmc_base-config);
+ writel(config, gpmc_cfg-config);
/*
* Disable the GPMC0 config set by ROM code
* It conflicts with our MPDB (both at 0x0800)
*/
- writel(0, gpmc_base-cs[0].config7);
+ writel(0, gpmc_cfg-cs[0].config7);
sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */
gpmc_config = gpmc_m_nand;
- gpmc_cfg = gpmc_base;
base = PISMO1_NAND_BASE;
size = PISMO1_NAND_SIZE;
- enable_gpmc_cs_config(gpmc_config, gpmc_base-cs[0], base, size);
+ enable_gpmc_cs_config(gpmc_config, gpmc_cfg-cs[0], base, size);
#if defined(CONFIG_ENV_IS_IN_NAND)
f_off = SMNAND_ENV_OFFSET;
f_sec = SZ_128K;
@@ -263,7 +262,7 @@ void gpmc_init(void)
gpmc_config = gpmc_onenand;
base = PISMO1_ONEN_BASE;
size = PISMO1_ONEN_SIZE;
- enable_gpmc_cs_config(gpmc_config, gpmc_base-cs[0], base, size);
+ enable_gpmc_cs_config(gpmc_config, gpmc_cfg-cs[0], base, size);
#if defined(CONFIG_ENV_IS_IN_ONENAND)
f_off = ONENAND_ENV_OFFSET;
f_sec = SZ_128K;
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c
b/cpu/arm_cortexa8/omap3/sys_info.c
index e0e5153..765aaf2 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -32,7 +32,6 @@
#include i2c.h
extern omap3_sysinfo sysinfo;
-static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
static char *rev_s[CPU_3XX_MAX_REV] = {
@@ -160,7 +159,7 @@ u32 get_gpmc0_base(void)
{
u32 b;
- b = readl(gpmc_base-cs[0].config7);
+ b = readl(gpmc_cfg-cs[0].config7);
b = 0x1F; /* keep base
