Re: [U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
Hello,
On 15-04-09 18:09:46, Marek Vasut wrote:
On Tuesday, April 07, 2015 at 09:03:45 AM, maitysancha...@gmail.com wrote:
Hello,
On 15-04-01 21:15:21, Marek Vasut wrote:
On Wednesday, April 01, 2015 at 11:54:22 AM, Sanchayan Maity wrote:
The commit message is missing, please fix in v2.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
[...]
+#define USB_NC_REG_OFFSET 0x0800
+#define USBCx_CTRL_OFFSET 0x
+#define USBCx_PHY_CTRL_OFFSET 0x0018
Please define the register offsets using the regular struct {} method,
see for example struct mxs_usbphy_regs and it's usage in ehci-mxs.c .
I had a query here, just to be sure and avoid rework. The vybrid defines
would be similar to mxs. I assume I can add them to the regs-common.h
file along with a note that the VF610 also has the same _set, _clr,
_tog register? Or perhaps it would be more appropriate to have the file
have generic names which mxs, vf and imx can all leverage? Though for
now this would require reworking all the three drivers.
The USB phy definitions part is ok, as they would go in the arch
specific folder.
If these are really IMX/MXS/VF specific, then the defines should go into
arch/arm/include/asm/imx-common/ . Otherwise, you can make chipidea specific
file in include/usb/ .
Not really much VF specific. I was not sure about using the mxs_ prefix
accessors for VF as well. In the end I found usage in one iMX6 file and
decided that it makes better sense to actually use the mxs_ existing
defines. They can be used for Vybrid as well. Except for the non core
regsiters and a few others no other difference.
I send a v2 version of the patchset based taking your suggestion into
account. The driver looks cleaner in comparison to the previous :)
IMHO. Thanks.
https://www.mail-archive.com/u-boot@lists.denx.de/msg168727.html
- Sanchayan.
+#define USBPHY_CTRL
0x0030
+#define USBPHY_CTRL_SET
0x0034
+#define USBPHY_CTRL_CLR
0x0038
+#define USBPHY_CTRL_TOG
0x003c
+
+#define USBPHY_PWD
0x
+#define USBPHY_TX
0x0010
+#define USBPHY_RX
0x0020
+#define USBPHY_DEBUG 0x0050
+#define USBPHY_CTRL_SFTRST 0x8000
+#define USBPHY_CTRL_CLKGATE0x4000
+#define USBPHY_CTRL_ENUTMILEVEL3 0x8000
+#define USBPHY_CTRL_ENUTMILEVEL2 0x4000
+#define USBPHY_CTRL_OTG_ID 0x0800
+
+#define ANADIG_PLL_CTRL_BYPASS 0x0001
+#define ANADIG_PLL_CTRL_ENABLE 0x2000
+#define ANADIG_PLL_CTRL_POWER 0x1000
+#define ANADIG_PLL_CTRL_EN_USB_CLKS0x0040
+
+#define UCTRL_OVER_CUR_POL (1 8) /* OTG Polarity of Overcurrent
*/
+#define UCTRL_OVER_CUR_DIS (1 7) /* Disable OTG Overcurrent
Detection */ +
+/* USBCMD */
+#define UCMD_RUN_STOP (1 0) /* controller run/stop */
+#define UCMD_RESET (1 1) /* controller reset */
This looks very much like the USB PHY used on MX28 , can you double-check
this please ?
MX28 IP also seems similar to the Vybrid USB IP except for a few
registers and the non core registers. Perhaps to be expected as they all
have a common chipidea IP core, though having a different version
thereof.
Yep, I agree :)
Thanks!
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Re: [U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
On Tuesday, April 07, 2015 at 09:03:45 AM, maitysancha...@gmail.com wrote:
Hello,
On 15-04-01 21:15:21, Marek Vasut wrote:
On Wednesday, April 01, 2015 at 11:54:22 AM, Sanchayan Maity wrote:
The commit message is missing, please fix in v2.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
[...]
+#define USB_NC_REG_OFFSET0x0800
+#define USBCx_CTRL_OFFSET0x
+#define USBCx_PHY_CTRL_OFFSET0x0018
Please define the register offsets using the regular struct {} method,
see for example struct mxs_usbphy_regs and it's usage in ehci-mxs.c .
I had a query here, just to be sure and avoid rework. The vybrid defines
would be similar to mxs. I assume I can add them to the regs-common.h
file along with a note that the VF610 also has the same _set, _clr,
_tog register? Or perhaps it would be more appropriate to have the file
have generic names which mxs, vf and imx can all leverage? Though for
now this would require reworking all the three drivers.
The USB phy definitions part is ok, as they would go in the arch
specific folder.
If these are really IMX/MXS/VF specific, then the defines should go into
arch/arm/include/asm/imx-common/ . Otherwise, you can make chipidea specific
file in include/usb/ .
+#define USBPHY_CTRL
0x0030
+#define USBPHY_CTRL_SET 0x0034
+#define USBPHY_CTRL_CLR 0x0038
+#define USBPHY_CTRL_TOG 0x003c
+
+#define USBPHY_PWD
0x
+#define USBPHY_TX
0x0010
+#define USBPHY_RX
0x0020
+#define USBPHY_DEBUG 0x0050
+#define USBPHY_CTRL_SFTRST 0x8000
+#define USBPHY_CTRL_CLKGATE 0x4000
+#define USBPHY_CTRL_ENUTMILEVEL3 0x8000
+#define USBPHY_CTRL_ENUTMILEVEL2 0x4000
+#define USBPHY_CTRL_OTG_ID 0x0800
+
+#define ANADIG_PLL_CTRL_BYPASS 0x0001
+#define ANADIG_PLL_CTRL_ENABLE 0x2000
+#define ANADIG_PLL_CTRL_POWER0x1000
+#define ANADIG_PLL_CTRL_EN_USB_CLKS 0x0040
+
+#define UCTRL_OVER_CUR_POL (1 8) /* OTG Polarity of Overcurrent
*/
+#define UCTRL_OVER_CUR_DIS (1 7) /* Disable OTG Overcurrent
Detection */ +
+/* USBCMD */
+#define UCMD_RUN_STOP(1 0) /* controller run/stop */
+#define UCMD_RESET (1 1) /* controller reset */
This looks very much like the USB PHY used on MX28 , can you double-check
this please ?
MX28 IP also seems similar to the Vybrid USB IP except for a few
registers and the non core registers. Perhaps to be expected as they all
have a common chipidea IP core, though having a different version
thereof.
Yep, I agree :)
Thanks!
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Re: [U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
Hi Marek,
On Wed, Apr 1, 2015 at 4:15 PM, Marek Vasut ma...@denx.de wrote:
+#define USB_NC_REG_OFFSET0x0800
+#define USBCx_CTRL_OFFSET0x
+#define USBCx_PHY_CTRL_OFFSET0x0018
Please define the register offsets using the regular struct {} method,
see for example struct mxs_usbphy_regs and it's usage in ehci-mxs.c .
I thought we were trying to get rid of the 'no register access via
offset' rule in U-boot.
https://www.marc.info/?l=u-bootm=142609602127309w=2
Please see:
Regards,
Fabio Estevam
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Re: [U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
Hello,
On 15-04-01 21:15:21, Marek Vasut wrote:
On Wednesday, April 01, 2015 at 11:54:22 AM, Sanchayan Maity wrote:
The commit message is missing, please fix in v2.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
[...]
+#define USB_NC_REG_OFFSET 0x0800
+#define USBCx_CTRL_OFFSET 0x
+#define USBCx_PHY_CTRL_OFFSET 0x0018
Please define the register offsets using the regular struct {} method,
see for example struct mxs_usbphy_regs and it's usage in ehci-mxs.c .
I had a query here, just to be sure and avoid rework. The vybrid defines
would be similar to mxs. I assume I can add them to the regs-common.h
file along with a note that the VF610 also has the same _set, _clr,
_tog register? Or perhaps it would be more appropriate to have the file
have generic names which mxs, vf and imx can all leverage? Though for
now this would require reworking all the three drivers.
The USB phy definitions part is ok, as they would go in the arch
specific folder.
Thoughts?
+#define USBPHY_CTRL
0x0030
+#define USBPHY_CTRL_SET0x0034
+#define USBPHY_CTRL_CLR0x0038
+#define USBPHY_CTRL_TOG0x003c
+
+#define USBPHY_PWD 0x
+#define USBPHY_TX 0x0010
+#define USBPHY_RX 0x0020
+#define USBPHY_DEBUG 0x0050
+#define USBPHY_CTRL_SFTRST 0x8000
+#define USBPHY_CTRL_CLKGATE0x4000
+#define USBPHY_CTRL_ENUTMILEVEL3 0x8000
+#define USBPHY_CTRL_ENUTMILEVEL2 0x4000
+#define USBPHY_CTRL_OTG_ID 0x0800
+
+#define ANADIG_PLL_CTRL_BYPASS 0x0001
+#define ANADIG_PLL_CTRL_ENABLE 0x2000
+#define ANADIG_PLL_CTRL_POWER 0x1000
+#define ANADIG_PLL_CTRL_EN_USB_CLKS0x0040
+
+#define UCTRL_OVER_CUR_POL (1 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS (1 7) /* Disable OTG Overcurrent Detection
*/ +
+/* USBCMD */
+#define UCMD_RUN_STOP (1 0) /* controller run/stop */
+#define UCMD_RESET (1 1) /* controller reset */
This looks very much like the USB PHY used on MX28 , can you double-check this
please ?
MX28 IP also seems similar to the Vybrid USB IP except for a few
registers and the non core registers. Perhaps to be expected as they all
have a common chipidea IP core, though having a different version
thereof.
Best regards,
Marek Vasut
- Sanchayan.
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Re: [U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
Hello,
On 15-04-01 21:15:21, Marek Vasut wrote:
On Wednesday, April 01, 2015 at 11:54:22 AM, Sanchayan Maity wrote:
The commit message is missing, please fix in v2.
Ok. Will add the commit message in v2.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
[...]
+#define USB_NC_REG_OFFSET 0x0800
+#define USBCx_CTRL_OFFSET 0x
+#define USBCx_PHY_CTRL_OFFSET 0x0018
Please define the register offsets using the regular struct {} method,
see for example struct mxs_usbphy_regs and it's usage in ehci-mxs.c .
Ok. Will fix in v2.
+#define USBPHY_CTRL
0x0030
+#define USBPHY_CTRL_SET0x0034
+#define USBPHY_CTRL_CLR0x0038
+#define USBPHY_CTRL_TOG0x003c
+
+#define USBPHY_PWD 0x
+#define USBPHY_TX 0x0010
+#define USBPHY_RX 0x0020
+#define USBPHY_DEBUG 0x0050
+#define USBPHY_CTRL_SFTRST 0x8000
+#define USBPHY_CTRL_CLKGATE0x4000
+#define USBPHY_CTRL_ENUTMILEVEL3 0x8000
+#define USBPHY_CTRL_ENUTMILEVEL2 0x4000
+#define USBPHY_CTRL_OTG_ID 0x0800
+
+#define ANADIG_PLL_CTRL_BYPASS 0x0001
+#define ANADIG_PLL_CTRL_ENABLE 0x2000
+#define ANADIG_PLL_CTRL_POWER 0x1000
+#define ANADIG_PLL_CTRL_EN_USB_CLKS0x0040
+
+#define UCTRL_OVER_CUR_POL (1 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS (1 7) /* Disable OTG Overcurrent Detection
*/ +
+/* USBCMD */
+#define UCMD_RUN_STOP (1 0) /* controller run/stop */
+#define UCMD_RESET (1 1) /* controller reset */
This looks very much like the USB PHY used on MX28 , can you double-check this
please ?
I have not yet looked at MX28, but, the Vybrid USB IP is in fact very
similar to i.MX6, however, the non core registers are spread in two
different register areas. Will have a look at MX28 as well.
This ehci-vf driver is very closely based on ehci-mx6 driver already in
uboot.
Best regards,
Marek Vasut
- Sanchayan.
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Re: [U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
On Thursday, April 02, 2015 at 12:55:57 PM, maitysancha...@gmail.com wrote: Hello, Hi! [...] +#define UCTRL_OVER_CUR_DIS (1 7) /* Disable OTG Overcurrent Detection */ + +/* USBCMD */ +#define UCMD_RUN_STOP(1 0) /* controller run/stop */ +#define UCMD_RESET (1 1) /* controller reset */ This looks very much like the USB PHY used on MX28 , can you double-check this please ? I have not yet looked at MX28, but, the Vybrid USB IP is in fact very similar to i.MX6, however, the non core registers are spread in two different register areas. Will have a look at MX28 as well. This ehci-vf driver is very closely based on ehci-mx6 driver already in uboot. Understood, thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 14 ++
arch/arm/include/asm/arch-vf610/imx-regs.h | 4 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-vf.c | 204 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/usb/host/ehci-vf.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 78708e2..851c3b9 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -124,6 +124,10 @@ struct anadig_reg {
#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 16)
#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) 0x7) 16)
+#define CCM_CCSR_PLL3_PFD4_EN (1 31)
+#define CCM_CCSR_PLL3_PFD3_EN (1 30)
+#define CCM_CCSR_PLL3_PFD2_EN (1 29)
+#define CCM_CCSR_PLL3_PFD1_EN (1 28)
#define CCM_CCSR_PLL2_PFD4_EN (1 15)
#define CCM_CCSR_PLL2_PFD3_EN (1 14)
#define CCM_CCSR_PLL2_PFD2_EN (1 13)
@@ -189,6 +193,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0x
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 8)
@@ -207,14 +212,23 @@ struct anadig_reg {
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 8)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define ANADIG_PLL7_CTRL_BYPASS (1 16)
+#define ANADIG_PLL7_CTRL_ENABLE (1 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL5_CTRL_BYPASS (1 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 13)
#define ANADIG_PLL5_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT1
+#define ANADIG_PLL3_CTRL_BYPASS (1 16)
+#define ANADIG_PLL3_CTRL_ENABLE (1 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL2_CTRL_ENABLE(1 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT1
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index a5908ca..26057fe 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -52,6 +52,7 @@
#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
@@ -65,6 +66,8 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
+#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
@@ -84,6 +87,7 @@
#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index eb6f34b..4bd9321 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
diff --git
Re: [U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
On Wednesday, April 01, 2015 at 11:54:22 AM, Sanchayan Maity wrote:
The commit message is missing, please fix in v2.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
[...]
+#define USB_NC_REG_OFFSET0x0800
+#define USBCx_CTRL_OFFSET0x
+#define USBCx_PHY_CTRL_OFFSET0x0018
Please define the register offsets using the regular struct {} method,
see for example struct mxs_usbphy_regs and it's usage in ehci-mxs.c .
+#define USBPHY_CTRL 0x0030
+#define USBPHY_CTRL_SET 0x0034
+#define USBPHY_CTRL_CLR 0x0038
+#define USBPHY_CTRL_TOG 0x003c
+
+#define USBPHY_PWD 0x
+#define USBPHY_TX0x0010
+#define USBPHY_RX0x0020
+#define USBPHY_DEBUG 0x0050
+#define USBPHY_CTRL_SFTRST 0x8000
+#define USBPHY_CTRL_CLKGATE 0x4000
+#define USBPHY_CTRL_ENUTMILEVEL3 0x8000
+#define USBPHY_CTRL_ENUTMILEVEL2 0x4000
+#define USBPHY_CTRL_OTG_ID 0x0800
+
+#define ANADIG_PLL_CTRL_BYPASS 0x0001
+#define ANADIG_PLL_CTRL_ENABLE 0x2000
+#define ANADIG_PLL_CTRL_POWER0x1000
+#define ANADIG_PLL_CTRL_EN_USB_CLKS 0x0040
+
+#define UCTRL_OVER_CUR_POL (1 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS (1 7) /* Disable OTG Overcurrent Detection
*/ +
+/* USBCMD */
+#define UCMD_RUN_STOP(1 0) /* controller run/stop */
+#define UCMD_RESET (1 1) /* controller reset */
This looks very much like the USB PHY used on MX28 , can you double-check this
please ?
Best regards,
Marek Vasut
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