Re: [U-Boot] [RESEND PATCH v3 2/2] keystone2: net: add keystone ethernet driver
>-Original Message- >From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Rini, Tom >Sent: Friday, March 28, 2014 11:50 AM >To: Karicheri, Muralidharan >Cc: u-boot@lists.denx.de; Kwok, WingMan >Subject: Re: [U-Boot] [RESEND PATCH v3 2/2] keystone2: net: add keystone >ethernet >driver > >On Fri, Mar 21, 2014 at 05:01:43PM -0400, Murali Karicheri wrote: > >> Ethernet driver configures the CPSW, SGMI and Phy and uses the the >> Navigator APIs. The driver supports 4 Ethernet ports and can work with >> only one port at a time. >> >> Port configurations are defined in board.c. >> >> Signed-off-by: Vitaly Andrianov >> Signed-off-by: Murali Karicheri >> Signed-off-by: WingMan Kwok >[snip] >> +#define reg_rmw(addr, value, mask) \ >> +writel(((readl(addr) & (~(mask))) | (value)), (addr)) > >Don't we have something in asm/io.h that does this already? > Tom, I did a scan of arch/arm/include/asm/io.h. I can't find a read/modify/write function. Am I missing something? Murali >-- >Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v3 2/2] keystone2: net: add keystone ethernet driver
On Fri, Mar 21, 2014 at 05:01:43PM -0400, Murali Karicheri wrote: > Ethernet driver configures the CPSW, SGMI and Phy and uses > the the Navigator APIs. The driver supports 4 Ethernet ports and > can work with only one port at a time. > > Port configurations are defined in board.c. > > Signed-off-by: Vitaly Andrianov > Signed-off-by: Murali Karicheri > Signed-off-by: WingMan Kwok [snip] > +#define reg_rmw(addr, value, mask) \ > + writel(((readl(addr) & (~(mask))) | (value)), (addr)) Don't we have something in asm/io.h that does this already? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCH v3 2/2] keystone2: net: add keystone ethernet driver
Ethernet driver configures the CPSW, SGMI and Phy and uses
the the Navigator APIs. The driver supports 4 Ethernet ports and
can work with only one port at a time.
Port configurations are defined in board.c.
Signed-off-by: Vitaly Andrianov
Signed-off-by: Murali Karicheri
Signed-off-by: WingMan Kwok
---
arch/arm/include/asm/arch-keystone/emac_defs.h | 240
board/ti/k2hk_evm/board.c | 65 +++
drivers/net/Makefile |1 +
drivers/net/keystone_net.c | 720
include/configs/k2hk_evm.h | 35 ++
5 files changed, 1061 insertions(+)
create mode 100644 arch/arm/include/asm/arch-keystone/emac_defs.h
create mode 100644 drivers/net/keystone_net.c
diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h
b/arch/arm/include/asm/arch-keystone/emac_defs.h
new file mode 100644
index 000..0aa2f89
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/emac_defs.h
@@ -0,0 +1,240 @@
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated,
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EMAC_DEFS_H_
+#define _EMAC_DEFS_H_
+
+#include
+#include
+
+#define DEVICE_REG32_R(a) readl(a)
+#define DEVICE_REG32_W(a, v)writel(v, a)
+
+#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
+#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
+#define EMAC_SGMII_BASE_ADDR(KS2_PASS_BASE + 0x00090100)
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR(KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
+#ifdef CONFIG_SOC_K2HK
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ100/* 1.0 MHz */
+#endif
+
+/* MII Status Register */
+#define MII_STATUS_REG 1
+#define MII_STATUS_LINK_MASK(0x4)
+
+/* Marvell 88E PHY ID */
+#define PHY_MARVELL_88E (0x01410cc0)
+
+#define MDIO_CONTROL_IDLE (0x8000)
+#define MDIO_CONTROL_ENABLE (0x4000)
+#define MDIO_CONTROL_FAULT_ENABLE (0x4)
+#define MDIO_CONTROL_FAULT (0x8)
+#define MDIO_USERACCESS0_GO (0x8000)
+#define MDIO_USERACCESS0_WRITE_READ (0x0)
+#define MDIO_USERACCESS0_WRITE_WRITE(0x4000)
+#define MDIO_USERACCESS0_ACK(0x2000)
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
+#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
+#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
+#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
+
+struct mac_sl_cfg {
+ u_int32_t max_rx_len; /* Maximum receive packet length. */
+ u_int32_t ctl; /* Control bitfield */
+};
+
+/*
+ * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
+#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
+#define GMACSL_RX_ENABLE_GIG_FORCE(1 << 17)
+#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
+#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
+#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
+#define GMACSL_TX_ENABLE_SHORT_GAP(1 << 10)
+#define GMACSL_ENABLE_GIG_MODE(1 << 7)
+#define GMACSL_TX_ENABLE_PACE (1 << 6)
+#define GMACSL_ENABLE (1 << 5)
+#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
+#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
+#define GMACSL_ENABLE_LOOPBACK(1 << 1)
+#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
+
+/*
+ * DEFINTITION: function return values
+ */
+#define GMACSL_RET_OK0
+#define GMACSL_RET_INVALID_PORT -1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE-2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
+
+/* Register offsets */
+#define CPGMACSL_REG_ID 0x00
+#define CPGMACSL_REG_CTL0x04
+#define CPGMACSL_REG_STATUS 0x08
+#define CPGMACSL_REG_RESET 0x0c
+#define CPGMACSL_REG_MAXLEN 0x10
+#define CPGMACSL_REG_BOFF 0x14
+#define CPGMACSL_REG_RX_PAUSE 0x18
+#define CPGMACSL_REG_TX_PAURSE 0x1c
+#define CPGMACSL_REG_EM_CTL 0x20
+#define CPGMACSL_REG_PRI0x24
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
+#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
+
+/* Maxlen register values */
+#define CPGMAC_REG_MAXLEN_
