Re: [U-Boot] [RFC PATCH 3/8] clk: actions: Add common clock driver

2019-01-05 Thread Manivannan Sadhasivam 
On Thu, Jan 03, 2019 at 06:56:18PM +0530, Amit Singh Tomar wrote:
> CMU block on most of the actions SoC seems to be identical(S900,
> S700 and S500)?
>

No :-) S500 is slightly different from S900/S700 but I will tackle this
later.

> This patch converts S900 clock driver to something common that can
> be used for other SoCs, for instance S700(most of clk registres are same).
> 
> Signed-off-by: Amit Singh Tomar 
> ---
>  arch/arm/include/asm/arch-owl/clk_owl.h   |  61 +
>  arch/arm/include/asm/arch-owl/clk_s900.h  |  57 -
>  arch/arm/include/asm/arch-owl/regs_s700.h |  56 
>  drivers/clk/owl/Kconfig   |   8 +-
>  drivers/clk/owl/Makefile  |   2 +-
>  drivers/clk/owl/clk_owl.c | 132 
>  drivers/clk/owl/clk_s900.c| 137 
> --
>  7 files changed, 252 insertions(+), 201 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h
>  delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h
>  create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h
>  create mode 100644 drivers/clk/owl/clk_owl.c
>  delete mode 100644 drivers/clk/owl/clk_s900.c
> 
> diff --git a/arch/arm/include/asm/arch-owl/clk_owl.h 
> b/arch/arm/include/asm/arch-owl/clk_owl.h
> new file mode 100644
> index 000..8ff7537
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-owl/clk_owl.h
> @@ -0,0 +1,61 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Actions Semi S900 Clock Definitions
> + *
> + * Copyright (C) 2015 Actions Semi Co., Ltd.
> + * Copyright (C) 2018 Manivannan Sadhasivam 
> 
> + *
> + */
> +
> +#ifndef _OWL_CLK_H_
> +#define _OWL_CLK_H_
> +
> +#include 
> +
> +struct owl_clk_priv {
> + phys_addr_t base;
> +};
> +
> +/* BUSCLK register definitions */
> +#define CMU_PDBGDIV_87
> +#define CMU_PDBGDIV_SHIFT26
> +#define CMU_PDBGDIV_DIV  (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
> +#define CMU_PERDIV_8 7
> +#define CMU_PERDIV_SHIFT 20
> +#define CMU_PERDIV_DIV   (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
> +#define CMU_NOCDIV_2 1
> +#define CMU_NOCDIV_SHIFT 19
> +#define CMU_NOCDIV_DIV   (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
> +#define CMU_DMMCLK_SRC_APLL  2
> +#define CMU_DMMCLK_SRC_SHIFT 10
> +#define CMU_DMMCLK_SRC   (CMU_DMMCLK_SRC_APLL << 
> CMU_DMMCLK_SRC_SHIFT)
> +#define CMU_APBCLK_DIV   BIT(8)
> +#define CMU_NOCCLK_SRC   BIT(7)
> +#define CMU_AHBCLK_DIV   BIT(4)
> +#define CMU_CORECLK_MASK 3
> +#define CMU_CORECLK_CPLL BIT(1)
> +#define CMU_CORECLK_HOSC BIT(0)
> +
> +/* COREPLL register definitions */
> +#define CMU_COREPLL_EN   BIT(9)
> +#define CMU_COREPLL_HOSC_EN  BIT(8)
> +#define CMU_COREPLL_OUT  (1104 / 24)
> +
> +/* DEVPLL register definitions */
> +#define CMU_DEVPLL_CLK   BIT(12)
> +#define CMU_DEVPLL_ENBIT(8)
> +#define CMU_DEVPLL_OUT   (660 / 6)
> +
> +/* UARTCLK register definitions */
> +#define CMU_UARTCLK_SRC_DEVPLL   BIT(16)
> +
> +/* DEVCLKEN1 register definitions */
> +#if defined(CONFIG_MACH_S900)
> +#define CMU_DEVCLKEN1_UART5  BIT(21)
> +#elif defined(CONFIG_MACH_S700)
> +#define CMU_DEVCLKEN1_UART3 BIT(11)
> +#endif
> +
> +#define PLL_STABILITY_WAIT_US50
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h 
> b/arch/arm/include/asm/arch-owl/clk_s900.h
> deleted file mode 100644
> index 88e88f7..000
> --- a/arch/arm/include/asm/arch-owl/clk_s900.h
> +++ /dev/null
> @@ -1,57 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Actions Semi S900 Clock Definitions
> - *
> - * Copyright (C) 2015 Actions Semi Co., Ltd.
> - * Copyright (C) 2018 Manivannan Sadhasivam 
> 
> - *
> - */
> -
> -#ifndef _OWL_CLK_S900_H_
> -#define _OWL_CLK_S900_H_
> -
> -#include 
> -
> -struct owl_clk_priv {
> - phys_addr_t base;
> -};
> -
> -/* BUSCLK register definitions */
> -#define CMU_PDBGDIV_87
> -#define CMU_PDBGDIV_SHIFT26
> -#define CMU_PDBGDIV_DIV  (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
> -#define CMU_PERDIV_8 7
> -#define CMU_PERDIV_SHIFT 20
> -#define CMU_PERDIV_DIV   (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
> -#define CMU_NOCDIV_2 1
> -#define CMU_NOCDIV_SHIFT 19
> -#define CMU_NOCDIV_DIV   (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
> -#define CMU_DMMCLK_SRC_APLL  2
> -#define CMU_DMMCLK_SRC_SHIFT 10
> -#define CMU_DMMCLK_SRC   (CMU_DMMCLK_SRC_APLL << 
> CMU_DMMCLK_SRC_SHIFT)
> -#define CMU_APBCLK_DIV   BIT(8)
> -#define CMU_NOCCLK_SRC   BIT(7)
> -#define CMU_AHBCLK_DIV   BIT(4)
> -#define CMU_CORECLK_MASK 3
> -#define CMU_CORECLK_CPLL BIT(1)
> -#define CMU_CORECLK_HOSC BIT(0)
> -
> -/* COREPLL register definitions */
> -#define CMU_COREPLL_EN   BIT(9)
> -#define

[U-Boot] [RFC PATCH 3/8] clk: actions: Add common clock driver

2019-01-03 Thread Amit Singh Tomar 
CMU block on most of the actions SoC seems to be identical(S900,
S700 and S500)?

This patch converts S900 clock driver to something common that can
be used for other SoCs, for instance S700(most of clk registres are same).

Signed-off-by: Amit Singh Tomar 
---
 arch/arm/include/asm/arch-owl/clk_owl.h   |  61 +
 arch/arm/include/asm/arch-owl/clk_s900.h  |  57 -
 arch/arm/include/asm/arch-owl/regs_s700.h |  56 
 drivers/clk/owl/Kconfig   |   8 +-
 drivers/clk/owl/Makefile  |   2 +-
 drivers/clk/owl/clk_owl.c | 132 
 drivers/clk/owl/clk_s900.c| 137 --
 7 files changed, 252 insertions(+), 201 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h
 delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h
 create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h
 create mode 100644 drivers/clk/owl/clk_owl.c
 delete mode 100644 drivers/clk/owl/clk_s900.c

diff --git a/arch/arm/include/asm/arch-owl/clk_owl.h 
b/arch/arm/include/asm/arch-owl/clk_owl.h
new file mode 100644
index 000..8ff7537
--- /dev/null
+++ b/arch/arm/include/asm/arch-owl/clk_owl.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi S900 Clock Definitions
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam 
+ *
+ */
+
+#ifndef _OWL_CLK_H_
+#define _OWL_CLK_H_
+
+#include 
+
+struct owl_clk_priv {
+   phys_addr_t base;
+};
+
+/* BUSCLK register definitions */
+#define CMU_PDBGDIV_8  7
+#define CMU_PDBGDIV_SHIFT  26
+#define CMU_PDBGDIV_DIV(CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
+#define CMU_PERDIV_8   7
+#define CMU_PERDIV_SHIFT   20
+#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
+#define CMU_NOCDIV_2   1
+#define CMU_NOCDIV_SHIFT   19
+#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
+#define CMU_DMMCLK_SRC_APLL2
+#define CMU_DMMCLK_SRC_SHIFT   10
+#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
+#define CMU_APBCLK_DIV BIT(8)
+#define CMU_NOCCLK_SRC BIT(7)
+#define CMU_AHBCLK_DIV BIT(4)
+#define CMU_CORECLK_MASK   3
+#define CMU_CORECLK_CPLL   BIT(1)
+#define CMU_CORECLK_HOSC   BIT(0)
+
+/* COREPLL register definitions */
+#define CMU_COREPLL_EN BIT(9)
+#define CMU_COREPLL_HOSC_ENBIT(8)
+#define CMU_COREPLL_OUT(1104 / 24)
+
+/* DEVPLL register definitions */
+#define CMU_DEVPLL_CLK BIT(12)
+#define CMU_DEVPLL_EN  BIT(8)
+#define CMU_DEVPLL_OUT (660 / 6)
+
+/* UARTCLK register definitions */
+#define CMU_UARTCLK_SRC_DEVPLL BIT(16)
+
+/* DEVCLKEN1 register definitions */
+#if defined(CONFIG_MACH_S900)
+#define CMU_DEVCLKEN1_UART5BIT(21)
+#elif defined(CONFIG_MACH_S700)
+#define CMU_DEVCLKEN1_UART3 BIT(11)
+#endif
+
+#define PLL_STABILITY_WAIT_US  50
+
+#endif
diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h 
b/arch/arm/include/asm/arch-owl/clk_s900.h
deleted file mode 100644
index 88e88f7..000
--- a/arch/arm/include/asm/arch-owl/clk_s900.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Actions Semi S900 Clock Definitions
- *
- * Copyright (C) 2015 Actions Semi Co., Ltd.
- * Copyright (C) 2018 Manivannan Sadhasivam 
- *
- */
-
-#ifndef _OWL_CLK_S900_H_
-#define _OWL_CLK_S900_H_
-
-#include 
-
-struct owl_clk_priv {
-   phys_addr_t base;
-};
-
-/* BUSCLK register definitions */
-#define CMU_PDBGDIV_8  7
-#define CMU_PDBGDIV_SHIFT  26
-#define CMU_PDBGDIV_DIV(CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
-#define CMU_PERDIV_8   7
-#define CMU_PERDIV_SHIFT   20
-#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
-#define CMU_NOCDIV_2   1
-#define CMU_NOCDIV_SHIFT   19
-#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
-#define CMU_DMMCLK_SRC_APLL2
-#define CMU_DMMCLK_SRC_SHIFT   10
-#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
-#define CMU_APBCLK_DIV BIT(8)
-#define CMU_NOCCLK_SRC BIT(7)
-#define CMU_AHBCLK_DIV BIT(4)
-#define CMU_CORECLK_MASK   3
-#define CMU_CORECLK_CPLL   BIT(1)
-#define CMU_CORECLK_HOSC   BIT(0)
-
-/* COREPLL register definitions */
-#define CMU_COREPLL_EN BIT(9)
-#define CMU_COREPLL_HOSC_ENBIT(8)
-#define CMU_COREPLL_OUT(1104 / 24)
-
-/* DEVPLL register definitions */
-#define CMU_DEVPLL_CLK BIT(12)
-#define CMU_DEVPLL_EN  BIT(8)
-#define CMU_DEVPLL_OUT (660 / 6)
-
-/* UARTCLK register definitions */
-#define CMU_UARTCLK_SRC_DEVPLL BIT(16)
-
-/* DEVCLKEN1 register definitions */
-#define CMU_DEVCLKEN1_UART5BIT(21)
-
-#define PLL_STABILITY_WAIT_US  50
-
-#endif
diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h