Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Sunday 06 October 2013 09:00 PM, Jagan Teki wrote:
On Sun, Oct 6, 2013 at 3:44 PM, Sourav Poddar wrote:
On Sunday 06 October 2013 02:14 PM, Jagan Teki wrote:
What if this code is placed in cs_active() with BEGIN flag.?
+ /* setup command reg */
+ qslave->cmd = 0;
+ qslave->cmd |= QSPI_WLEN(8);
+ qslave->cmd |= QSPI_EN_CS(slave->cs);
+ if (flags& SPI_3WIRE)
+ qslave->cmd |= QSPI_3_PIN;
+ qslave->cmd |= 0xfff;
Functionality wise it wont effect. I am open to what you
suggest here, whether to move it or not.
Though, just one thing you should note here, is that the
above code just mask the cmd register bits. The actual
cmd register write happens inside while loop and only when
that write happens, then the cs gets activated.
So, above code does not activate the cs, it just prepare the mask
that will enable cs later.
OK, just park this as of now try to send next level patch-set we will
discuss more.
Ok. I am working on the next version.
On Sat, Oct 5, 2013 at 7:53 PM, Sourav Poddar
wrote:
On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddar
wrote:
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav
Poddar
wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized
in
0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went
wrong,
I
will check.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1<< 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n<< 28)
+#define QSPI_WLEN(n) ((n-1)<< 19)
+#define QSPI_3_PIN (1<< 18)
+#define QSPI_RD_SNGL (1<< 16)
+#define QSPI_WR_SNGL (2<< 16)
+#define QSPI_INVAL (4<< 16)
+#define QSPI_RD_QUAD (7<< 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m<< (3 + n*8))
+#define QSPI_CKPHA(n) (1<< (2 + n*8))
+#define QSPI_CSPOL(n) (1<< (1 + n*8))
+#define QSPI_CKPOL(n) (1<< (n*8))
+
+/* Status */
+#define QSPI_WC(1<< 1)
+#define QSPI_BUSY (1<< 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_X
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Sun, Oct 6, 2013 at 3:44 PM, Sourav Poddar wrote:
> On Sunday 06 October 2013 02:14 PM, Jagan Teki wrote:
>>
>> What if this code is placed in cs_active() with BEGIN flag.?
> + /* setup command reg */
>> + qslave->cmd = 0;
>> + qslave->cmd |= QSPI_WLEN(8);
>> + qslave->cmd |= QSPI_EN_CS(slave->cs);
>> + if (flags& SPI_3WIRE)
>> + qslave->cmd |= QSPI_3_PIN;
>> + qslave->cmd |= 0xfff;
>
> Functionality wise it wont effect. I am open to what you
> suggest here, whether to move it or not.
>
> Though, just one thing you should note here, is that the
> above code just mask the cmd register bits. The actual
> cmd register write happens inside while loop and only when
> that write happens, then the cs gets activated.
> So, above code does not activate the cs, it just prepare the mask
> that will enable cs later.
OK, just park this as of now try to send next level patch-set we will
discuss more.
>
>> On Sat, Oct 5, 2013 at 7:53 PM, Sourav Poddar
>> wrote:
>>>
>>> On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddar
wrote:
>
> On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
>>
>> On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar
>> wrote:
>>>
>>> On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
wrote:
>
> On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
>>
>> On Fri, Oct 4, 2013 at 8:21 PM, Sourav
>> Poddar
>> wrote:
>>>
>>> From: Matt Porter
>>>
>>> Adds a SPI master driver for the TI QSPI peripheral.
>>>
>>> Signed-off-by: Matt Porter
>>> Signed-off-by: Sourav Poddar
>>> [Added quad read support and memory mapped support).
>>
>> What is this comment, any specific?
>
> This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
>>> ---
>>
>> You missed change log for all patches, i think you have summarized
>> in
>> 0/6.
>> I feel it's better write it on individual patches.
>>
> Ok.
>
>>> drivers/spi/Makefile |1 +
>>> drivers/spi/ti_qspi.c | 328
>>> +
>>> 2 files changed, 329 insertions(+), 0 deletions(-)
>>> create mode 100644 drivers/spi/ti_qspi.c
>>>
>>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>>> index 91d24ce..e5941b0 100644
>>> --- a/drivers/spi/Makefile
>>> +++ b/drivers/spi/Makefile
>>> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
>>> COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
>>> COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
>>> COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
>>> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
>>> COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>>> COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>>>
>>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>>> new file mode 100644
>>> index 000..d8a03a8
>>> --- /dev/null
>>> +++ b/drivers/spi/ti_qspi.c
>>> @@ -0,0 +1,328 @@
>>> +/*
>>> + * TI QSPI driver
>>> + *
>>> + * Copyright (C) 2013, Texas Instruments, Incorporated
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>
>> Got below format after apply this patch - please check
>> *Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
>>
> ahh..I copied it from a patch on some list. May be something went
> wrong,
> I
> will check.
>
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +struct qspi_regs {
>>> +u32 pid;
>>> +u32 pad0[3];
>>> +u32 sysconfig;
>>> +u32 pad1[3];
>>> +u32 intr_status_raw_set;
>>> +u32 intr_status_enabled_clear;
>>> +u32 intr_enable_set;
>>> +u32 intr_enable_clear;
>>> +u32 intc_eoi;
>>> +u32 pad2[3];
>>> +u32 spi_clock_cntrl;
>>> +u32 spi_dc;
>>> +u32 spi_cmd;
>>> +u32 spi_status;
>>> +u32 spi_data;
>>> +u32 spi_setup0;
>>> +u32 spi_setup1;
>>> +u32 spi_setup2;
>>> +u32 spi_setup3;
>>> +u32 spi_switch;
>>> +u32 spi_data1;
>>> +u32 spi_data2;
>>> +u32 spi_data3;
>>
>> Please add tab space.
>>
> ok
>
>>> +};
>>> +
>>> +struct
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Sunday 06 October 2013 02:14 PM, Jagan Teki wrote:
What if this code is placed in cs_active() with BEGIN flag.?
+ /* setup command reg */
+ qslave->cmd = 0;
+ qslave->cmd |= QSPI_WLEN(8);
+ qslave->cmd |= QSPI_EN_CS(slave->cs);
+ if (flags& SPI_3WIRE)
+ qslave->cmd |= QSPI_3_PIN;
+ qslave->cmd |= 0xfff;
Functionality wise it wont effect. I am open to what you
suggest here, whether to move it or not.
Though, just one thing you should note here, is that the
above code just mask the cmd register bits. The actual
cmd register write happens inside while loop and only when
that write happens, then the cs gets activated.
So, above code does not activate the cs, it just prepare the mask
that will enable cs later.
On Sat, Oct 5, 2013 at 7:53 PM, Sourav Poddar wrote:
On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddar
wrote:
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized
in
0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went
wrong,
I
will check.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1<< 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n<< 28)
+#define QSPI_WLEN(n) ((n-1)<< 19)
+#define QSPI_3_PIN (1<< 18)
+#define QSPI_RD_SNGL (1<< 16)
+#define QSPI_WR_SNGL (2<< 16)
+#define QSPI_INVAL (4<< 16)
+#define QSPI_RD_QUAD (7<< 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m<< (3 + n*8))
+#define QSPI_CKPHA(n) (1<< (2 + n*8))
+#define QSPI_CSPOL(n) (1<< (1 + n*8))
+#define QSPI_CKPOL(n) (1<< (n*8))
+
+/* Status */
+#define QSPI_WC(1<< 1)
+#define QSPI_BUSY (1<< 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTR
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
What if this code is placed in cs_active() with BEGIN flag.?
+ /* setup command reg */
+ qslave->cmd = 0;
+ qslave->cmd |= QSPI_WLEN(8);
+ qslave->cmd |= QSPI_EN_CS(slave->cs);
+ if (flags & SPI_3WIRE)
+ qslave->cmd |= QSPI_3_PIN;
+ qslave->cmd |= 0xfff;
On Sat, Oct 5, 2013 at 7:53 PM, Sourav Poddar wrote:
> On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
>>
>> On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddar
>> wrote:
>>>
>>> On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar
wrote:
>
> On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
>>
>> On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
>> wrote:
>>>
>>> On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
wrote:
>
> From: Matt Porter
>
> Adds a SPI master driver for the TI QSPI peripheral.
>
> Signed-off-by: Matt Porter
> Signed-off-by: Sourav Poddar
> [Added quad read support and memory mapped support).
What is this comment, any specific?
>>>
>>> This simply tell the portion which i did in the patch.
>>
>> May be not required, bcz it will come after i apply below s-o-b
>>
> ---
You missed change log for all patches, i think you have summarized
in
0/6.
I feel it's better write it on individual patches.
>>> Ok.
>>>
> drivers/spi/Makefile |1 +
> drivers/spi/ti_qspi.c | 328
> +
> 2 files changed, 329 insertions(+), 0 deletions(-)
> create mode 100644 drivers/spi/ti_qspi.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 91d24ce..e5941b0 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
> COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
> COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
> COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
> COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> new file mode 100644
> index 000..d8a03a8
> --- /dev/null
> +++ b/drivers/spi/ti_qspi.c
> @@ -0,0 +1,328 @@
> +/*
> + * TI QSPI driver
> + *
> + * Copyright (C) 2013, Texas Instruments, Incorporated
> + *
> + * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
>>> ahh..I copied it from a patch on some list. May be something went
>>> wrong,
>>> I
>>> will check.
>>>
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct qspi_regs {
> +u32 pid;
> +u32 pad0[3];
> +u32 sysconfig;
> +u32 pad1[3];
> +u32 intr_status_raw_set;
> +u32 intr_status_enabled_clear;
> +u32 intr_enable_set;
> +u32 intr_enable_clear;
> +u32 intc_eoi;
> +u32 pad2[3];
> +u32 spi_clock_cntrl;
> +u32 spi_dc;
> +u32 spi_cmd;
> +u32 spi_status;
> +u32 spi_data;
> +u32 spi_setup0;
> +u32 spi_setup1;
> +u32 spi_setup2;
> +u32 spi_setup3;
> +u32 spi_switch;
> +u32 spi_data1;
> +u32 spi_data2;
> +u32 spi_data3;
Please add tab space.
>>> ok
>>>
> +};
> +
> +struct qspi_slave {
> + struct spi_slave slave;
> + struct qspi_regs *base;
> + unsigned int mode;
> + u32 cmd;
> + u32 dc;
> +};
> +
-- TAG+
>
> +#define QSPI_TIMEOUT 200
> +
> +#define QSPI_FCLK 19200
> +
> +/* Clock Control */
> +#define QSPI_CLK_EN(1<< 31)
> +#define QSPI_CLK_DIV_MAX 0x
> +
> +/* Command */
> +#define QSPI_EN_CS(n) (n<< 28)
> +#define QSPI_WLEN(n) ((n-1)<< 19)
> +#define QSPI_3_PIN (1<< 18)
> +#define QSPI_RD_SNGL (1<< 16)
> +#define QSPI_WR_SNGL (2<< 16)
> +#define QSPI_INV
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddar wrote:
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized in
0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went
wrong,
I
will check.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1<< 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n<< 28)
+#define QSPI_WLEN(n) ((n-1)<< 19)
+#define QSPI_3_PIN (1<< 18)
+#define QSPI_RD_SNGL (1<< 16)
+#define QSPI_WR_SNGL (2<< 16)
+#define QSPI_INVAL (4<< 16)
+#define QSPI_RD_QUAD (7<< 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m<< (3 + n*8))
+#define QSPI_CKPHA(n) (1<< (2 + n*8))
+#define QSPI_CSPOL(n) (1<< (1 + n*8))
+#define QSPI_CKPOL(n) (1<< (n*8))
+
+/* Status */
+#define QSPI_WC(1<< 1)
+#define QSPI_BUSY (1<< 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3<< 0)
+#define QSPI_CMD_READ_QUAD (0x6b<< 0)
+#define QSPI_CMD_READ_FAST (0x0b<< 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2<< 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0<< 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1<< 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0<< 12)
+#define QSPI_SETUP0_READ_QUAD (0x3<< 12)
+#define QSPI_CMD_WRITE (0x2<< 16)
+#define QSPI_NUM_DUMMY_BITS(0x0<< 24)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
Ok.
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave
*slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline st
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddar wrote:
> On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
>>
>> On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar
>> wrote:
>>>
>>> On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
wrote:
>
> On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
>>
>> On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
>> wrote:
>>>
>>> From: Matt Porter
>>>
>>> Adds a SPI master driver for the TI QSPI peripheral.
>>>
>>> Signed-off-by: Matt Porter
>>> Signed-off-by: Sourav Poddar
>>> [Added quad read support and memory mapped support).
>>
>> What is this comment, any specific?
>
> This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
>>> ---
>>
>> You missed change log for all patches, i think you have summarized in
>> 0/6.
>> I feel it's better write it on individual patches.
>>
> Ok.
>
>>> drivers/spi/Makefile |1 +
>>> drivers/spi/ti_qspi.c | 328
>>> +
>>> 2 files changed, 329 insertions(+), 0 deletions(-)
>>> create mode 100644 drivers/spi/ti_qspi.c
>>>
>>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>>> index 91d24ce..e5941b0 100644
>>> --- a/drivers/spi/Makefile
>>> +++ b/drivers/spi/Makefile
>>> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
>>> COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
>>> COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
>>> COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
>>> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
>>> COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>>> COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>>>
>>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>>> new file mode 100644
>>> index 000..d8a03a8
>>> --- /dev/null
>>> +++ b/drivers/spi/ti_qspi.c
>>> @@ -0,0 +1,328 @@
>>> +/*
>>> + * TI QSPI driver
>>> + *
>>> + * Copyright (C) 2013, Texas Instruments, Incorporated
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>
>> Got below format after apply this patch - please check
>> *Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
>>
> ahh..I copied it from a patch on some list. May be something went
> wrong,
> I
> will check.
>
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +struct qspi_regs {
>>> +u32 pid;
>>> +u32 pad0[3];
>>> +u32 sysconfig;
>>> +u32 pad1[3];
>>> +u32 intr_status_raw_set;
>>> +u32 intr_status_enabled_clear;
>>> +u32 intr_enable_set;
>>> +u32 intr_enable_clear;
>>> +u32 intc_eoi;
>>> +u32 pad2[3];
>>> +u32 spi_clock_cntrl;
>>> +u32 spi_dc;
>>> +u32 spi_cmd;
>>> +u32 spi_status;
>>> +u32 spi_data;
>>> +u32 spi_setup0;
>>> +u32 spi_setup1;
>>> +u32 spi_setup2;
>>> +u32 spi_setup3;
>>> +u32 spi_switch;
>>> +u32 spi_data1;
>>> +u32 spi_data2;
>>> +u32 spi_data3;
>>
>> Please add tab space.
>>
> ok
>
>>> +};
>>> +
>>> +struct qspi_slave {
>>> + struct spi_slave slave;
>>> + struct qspi_regs *base;
>>> + unsigned int mode;
>>> + u32 cmd;
>>> + u32 dc;
>>> +};
>>> +
>>
>> -- TAG+
>>>
>>> +#define QSPI_TIMEOUT 200
>>> +
>>> +#define QSPI_FCLK 19200
>>> +
>>> +/* Clock Control */
>>> +#define QSPI_CLK_EN(1<<31)
>>> +#define QSPI_CLK_DIV_MAX 0x
>>> +
>>> +/* Command */
>>> +#define QSPI_EN_CS(n) (n<<28)
>>> +#define QSPI_WLEN(n) ((n-1)<<19)
>>> +#define QSPI_3_PIN (1<<18)
>>> +#define QSPI_RD_SNGL (1<<16)
>>> +#define QSPI_WR_SNGL (2<<16)
>>> +#define QSPI_INVAL (4<<16)
>>> +#define QSPI_RD_QUAD (7<<16)
>>> +
>>> +/* Device Control */
>>> +#define QSPI_DD(m, n) (m<<(3 + n*8))
>>> +#define QSPI_CKPHA(n) (1<<(2 + n*8))
>>> +#define QSPI_CSPOL(n) (1<<(1 + n*8))
>>> +#define QSPI_CKPOL(n) (1<<(n*8))
>>> +
>>> +/* Status */
>>> +#define QSPI_WC(1<<1)
>>> +#define QSPI_BUSY (1<<0)
>>> +#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
>>> +#define QSPI_XFER_DONE QSPI_WC
>>> +
>>> +#define MM_SWITCH
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized in
0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went wrong,
I
will check.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1<<31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n<<28)
+#define QSPI_WLEN(n) ((n-1)<<19)
+#define QSPI_3_PIN (1<<18)
+#define QSPI_RD_SNGL (1<<16)
+#define QSPI_WR_SNGL (2<<16)
+#define QSPI_INVAL (4<<16)
+#define QSPI_RD_QUAD (7<<16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m<<(3 + n*8))
+#define QSPI_CKPHA(n) (1<<(2 + n*8))
+#define QSPI_CSPOL(n) (1<<(1 + n*8))
+#define QSPI_CKPOL(n) (1<<(n*8))
+
+/* Status */
+#define QSPI_WC(1<<1)
+#define QSPI_BUSY (1<<0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3<<0)
+#define QSPI_CMD_READ_QUAD (0x6b<<0)
+#define QSPI_CMD_READ_FAST (0x0b<<0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2<<8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0<<10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1<<10)
+#define QSPI_SETUP0_READ_NORMAL(0x0<<12)
+#define QSPI_SETUP0_READ_QUAD (0x3<<12)
+#define QSPI_CMD_WRITE (0x2<<16)
+#define QSPI_NUM_DUMMY_BITS(0x0<<24)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
Ok.
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave
*slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline struct qspi_regs *get_qspi_bus(int dev)
+{
+ if (!dev)
+ return (struct qspi_regs *)QSPI_BASE;
+ else
+ ret
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar wrote:
> On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
>>
>> On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
>> wrote:
>>>
>>> On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
wrote:
>
> From: Matt Porter
>
> Adds a SPI master driver for the TI QSPI peripheral.
>
> Signed-off-by: Matt Porter
> Signed-off-by: Sourav Poddar
> [Added quad read support and memory mapped support).
What is this comment, any specific?
>>>
>>> This simply tell the portion which i did in the patch.
>>
>> May be not required, bcz it will come after i apply below s-o-b
>>
> ---
You missed change log for all patches, i think you have summarized in
0/6.
I feel it's better write it on individual patches.
>>> Ok.
>>>
>drivers/spi/Makefile |1 +
>drivers/spi/ti_qspi.c | 328
> +
>2 files changed, 329 insertions(+), 0 deletions(-)
>create mode 100644 drivers/spi/ti_qspi.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 91d24ce..e5941b0 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
>COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
>COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
>COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
>COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> new file mode 100644
> index 000..d8a03a8
> --- /dev/null
> +++ b/drivers/spi/ti_qspi.c
> @@ -0,0 +1,328 @@
> +/*
> + * TI QSPI driver
> + *
> + * Copyright (C) 2013, Texas Instruments, Incorporated
> + *
> + * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
>>> ahh..I copied it from a patch on some list. May be something went wrong,
>>> I
>>> will check.
>>>
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct qspi_regs {
> +u32 pid;
> +u32 pad0[3];
> +u32 sysconfig;
> +u32 pad1[3];
> +u32 intr_status_raw_set;
> +u32 intr_status_enabled_clear;
> +u32 intr_enable_set;
> +u32 intr_enable_clear;
> +u32 intc_eoi;
> +u32 pad2[3];
> +u32 spi_clock_cntrl;
> +u32 spi_dc;
> +u32 spi_cmd;
> +u32 spi_status;
> +u32 spi_data;
> +u32 spi_setup0;
> +u32 spi_setup1;
> +u32 spi_setup2;
> +u32 spi_setup3;
> +u32 spi_switch;
> +u32 spi_data1;
> +u32 spi_data2;
> +u32 spi_data3;
Please add tab space.
>>> ok
>>>
> +};
> +
> +struct qspi_slave {
> + struct spi_slave slave;
> + struct qspi_regs *base;
> + unsigned int mode;
> + u32 cmd;
> + u32 dc;
> +};
> +
-- TAG+
>
> +#define QSPI_TIMEOUT 200
> +
> +#define QSPI_FCLK 19200
> +
> +/* Clock Control */
> +#define QSPI_CLK_EN(1<< 31)
> +#define QSPI_CLK_DIV_MAX 0x
> +
> +/* Command */
> +#define QSPI_EN_CS(n) (n<< 28)
> +#define QSPI_WLEN(n) ((n-1)<< 19)
> +#define QSPI_3_PIN (1<< 18)
> +#define QSPI_RD_SNGL (1<< 16)
> +#define QSPI_WR_SNGL (2<< 16)
> +#define QSPI_INVAL (4<< 16)
> +#define QSPI_RD_QUAD (7<< 16)
> +
> +/* Device Control */
> +#define QSPI_DD(m, n) (m<< (3 + n*8))
> +#define QSPI_CKPHA(n) (1<< (2 + n*8))
> +#define QSPI_CSPOL(n) (1<< (1 + n*8))
> +#define QSPI_CKPOL(n) (1<< (n*8))
> +
> +/* Status */
> +#define QSPI_WC(1<< 1)
> +#define QSPI_BUSY (1<< 0)
> +#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
> +#define QSPI_XFER_DONE QSPI_WC
> +
> +#define MM_SWITCH 0x01
> +#define MEM_CS 0x100
> +#define MEM_CS_UNSELECT0xf0ff
> +#define MMAP_START_ADDR0x5c00
> +#define CORE_CTRL_IO 0x4a002558
> +
> +#define QSPI_CMD_READ (0x3<< 0)
> +#define QSPI_CMD_READ_QUAD (0x6b<< 0)
> +#define QSPI_CMD_READ_FAST (0x0b<< 0)
> +#define QSPI_SE
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized in 0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went wrong, I
will check.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1<< 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n<< 28)
+#define QSPI_WLEN(n) ((n-1)<< 19)
+#define QSPI_3_PIN (1<< 18)
+#define QSPI_RD_SNGL (1<< 16)
+#define QSPI_WR_SNGL (2<< 16)
+#define QSPI_INVAL (4<< 16)
+#define QSPI_RD_QUAD (7<< 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m<< (3 + n*8))
+#define QSPI_CKPHA(n) (1<< (2 + n*8))
+#define QSPI_CSPOL(n) (1<< (1 + n*8))
+#define QSPI_CKPOL(n) (1<< (n*8))
+
+/* Status */
+#define QSPI_WC(1<< 1)
+#define QSPI_BUSY (1<< 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3<< 0)
+#define QSPI_CMD_READ_QUAD (0x6b<< 0)
+#define QSPI_CMD_READ_FAST (0x0b<< 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2<< 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0<< 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1<< 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0<< 12)
+#define QSPI_SETUP0_READ_QUAD (0x3<< 12)
+#define QSPI_CMD_WRITE (0x2<< 16)
+#define QSPI_NUM_DUMMY_BITS(0x0<< 24)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
Ok.
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline struct qspi_regs *get_qspi_bus(int dev)
+{
+ if (!dev)
+ return (struct qspi_regs *)QSPI_BASE;
+ else
+ return NULL;
+}
Is this function really required, how many bus controller you have?
Actually one.
Ok, Please remove this function and assign direc
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar wrote:
> On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
>>
>> On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
>> wrote:
>>>
>>> From: Matt Porter
>>>
>>> Adds a SPI master driver for the TI QSPI peripheral.
>>>
>>> Signed-off-by: Matt Porter
>>> Signed-off-by: Sourav Poddar
>>> [Added quad read support and memory mapped support).
>>
>> What is this comment, any specific?
>
> This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
>
>>> ---
>>
>> You missed change log for all patches, i think you have summarized in 0/6.
>> I feel it's better write it on individual patches.
>>
> Ok.
>
>>> drivers/spi/Makefile |1 +
>>> drivers/spi/ti_qspi.c | 328
>>> +
>>> 2 files changed, 329 insertions(+), 0 deletions(-)
>>> create mode 100644 drivers/spi/ti_qspi.c
>>>
>>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>>> index 91d24ce..e5941b0 100644
>>> --- a/drivers/spi/Makefile
>>> +++ b/drivers/spi/Makefile
>>> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
>>> COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
>>> COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
>>> COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
>>> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
>>> COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>>> COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>>>
>>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>>> new file mode 100644
>>> index 000..d8a03a8
>>> --- /dev/null
>>> +++ b/drivers/spi/ti_qspi.c
>>> @@ -0,0 +1,328 @@
>>> +/*
>>> + * TI QSPI driver
>>> + *
>>> + * Copyright (C) 2013, Texas Instruments, Incorporated
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>
>> Got below format after apply this patch - please check
>> *Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
>>
> ahh..I copied it from a patch on some list. May be something went wrong, I
> will check.
>
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +struct qspi_regs {
>>> +u32 pid;
>>> +u32 pad0[3];
>>> +u32 sysconfig;
>>> +u32 pad1[3];
>>> +u32 intr_status_raw_set;
>>> +u32 intr_status_enabled_clear;
>>> +u32 intr_enable_set;
>>> +u32 intr_enable_clear;
>>> +u32 intc_eoi;
>>> +u32 pad2[3];
>>> +u32 spi_clock_cntrl;
>>> +u32 spi_dc;
>>> +u32 spi_cmd;
>>> +u32 spi_status;
>>> +u32 spi_data;
>>> +u32 spi_setup0;
>>> +u32 spi_setup1;
>>> +u32 spi_setup2;
>>> +u32 spi_setup3;
>>> +u32 spi_switch;
>>> +u32 spi_data1;
>>> +u32 spi_data2;
>>> +u32 spi_data3;
>>
>> Please add tab space.
>>
> ok
>
>>> +};
>>> +
>>> +struct qspi_slave {
>>> + struct spi_slave slave;
>>> + struct qspi_regs *base;
>>> + unsigned int mode;
>>> + u32 cmd;
>>> + u32 dc;
>>> +};
>>> +
>>
>> -- TAG+
>>>
>>> +#define QSPI_TIMEOUT 200
>>> +
>>> +#define QSPI_FCLK 19200
>>> +
>>> +/* Clock Control */
>>> +#define QSPI_CLK_EN(1<< 31)
>>> +#define QSPI_CLK_DIV_MAX 0x
>>> +
>>> +/* Command */
>>> +#define QSPI_EN_CS(n) (n<< 28)
>>> +#define QSPI_WLEN(n) ((n-1)<< 19)
>>> +#define QSPI_3_PIN (1<< 18)
>>> +#define QSPI_RD_SNGL (1<< 16)
>>> +#define QSPI_WR_SNGL (2<< 16)
>>> +#define QSPI_INVAL (4<< 16)
>>> +#define QSPI_RD_QUAD (7<< 16)
>>> +
>>> +/* Device Control */
>>> +#define QSPI_DD(m, n) (m<< (3 + n*8))
>>> +#define QSPI_CKPHA(n) (1<< (2 + n*8))
>>> +#define QSPI_CSPOL(n) (1<< (1 + n*8))
>>> +#define QSPI_CKPOL(n) (1<< (n*8))
>>> +
>>> +/* Status */
>>> +#define QSPI_WC(1<< 1)
>>> +#define QSPI_BUSY (1<< 0)
>>> +#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
>>> +#define QSPI_XFER_DONE QSPI_WC
>>> +
>>> +#define MM_SWITCH 0x01
>>> +#define MEM_CS 0x100
>>> +#define MEM_CS_UNSELECT0xf0ff
>>> +#define MMAP_START_ADDR0x5c00
>>> +#define CORE_CTRL_IO 0x4a002558
>>> +
>>> +#define QSPI_CMD_READ (0x3<< 0)
>>> +#define QSPI_CMD_READ_QUAD (0x6b<< 0)
>>> +#define QSPI_CMD_READ_FAST (0x0b<< 0)
>>> +#define QSPI_SETUP0_NUM_A_BYTES(0x2<< 8)
>>> +#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0<< 10)
>>> +#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1<< 10)
>>> +#define QSPI_SETUP0_READ_NORMAL(0x0<< 12)
>>> +#define QSPI_SETUP0_READ_QUAD (0x3<< 12)
>>> +#define QSPI_CMD_WRITE (0x2<< 16)
>>> +#define QSPI_NUM_DUMMY_BITS(0x0<< 24)
>>
>> --TAG-
>>
>> TAG+ ... TAG- please move these macro definitions i
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
---
You missed change log for all patches, i think you have summarized in 0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328 +
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went wrong, I
will check.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1<< 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n<< 28)
+#define QSPI_WLEN(n) ((n-1)<< 19)
+#define QSPI_3_PIN (1<< 18)
+#define QSPI_RD_SNGL (1<< 16)
+#define QSPI_WR_SNGL (2<< 16)
+#define QSPI_INVAL (4<< 16)
+#define QSPI_RD_QUAD (7<< 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m<< (3 + n*8))
+#define QSPI_CKPHA(n) (1<< (2 + n*8))
+#define QSPI_CSPOL(n) (1<< (1 + n*8))
+#define QSPI_CKPOL(n) (1<< (n*8))
+
+/* Status */
+#define QSPI_WC(1<< 1)
+#define QSPI_BUSY (1<< 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3<< 0)
+#define QSPI_CMD_READ_QUAD (0x6b<< 0)
+#define QSPI_CMD_READ_FAST (0x0b<< 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2<< 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0<< 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1<< 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0<< 12)
+#define QSPI_SETUP0_READ_QUAD (0x3<< 12)
+#define QSPI_CMD_WRITE (0x2<< 16)
+#define QSPI_NUM_DUMMY_BITS(0x0<< 24)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
Ok.
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline struct qspi_regs *get_qspi_bus(int dev)
+{
+ if (!dev)
+ return (struct qspi_regs *)QSPI_BASE;
+ else
+ return NULL;
+}
Is this function really required, how many bus controller you have?
Actually one.
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* CS handled i
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar wrote:
> From: Matt Porter
>
> Adds a SPI master driver for the TI QSPI peripheral.
>
> Signed-off-by: Matt Porter
> Signed-off-by: Sourav Poddar
> [Added quad read support and memory mapped support).
What is this comment, any specific?
> ---
You missed change log for all patches, i think you have summarized in 0/6.
I feel it's better write it on individual patches.
> drivers/spi/Makefile |1 +
> drivers/spi/ti_qspi.c | 328
> +
> 2 files changed, 329 insertions(+), 0 deletions(-)
> create mode 100644 drivers/spi/ti_qspi.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 91d24ce..e5941b0 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
> COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
> COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
> COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
> COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> new file mode 100644
> index 000..d8a03a8
> --- /dev/null
> +++ b/drivers/spi/ti_qspi.c
> @@ -0,0 +1,328 @@
> +/*
> + * TI QSPI driver
> + *
> + * Copyright (C) 2013, Texas Instruments, Incorporated
> + *
> + * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct qspi_regs {
> +u32 pid;
> +u32 pad0[3];
> +u32 sysconfig;
> +u32 pad1[3];
> +u32 intr_status_raw_set;
> +u32 intr_status_enabled_clear;
> +u32 intr_enable_set;
> +u32 intr_enable_clear;
> +u32 intc_eoi;
> +u32 pad2[3];
> +u32 spi_clock_cntrl;
> +u32 spi_dc;
> +u32 spi_cmd;
> +u32 spi_status;
> +u32 spi_data;
> +u32 spi_setup0;
> +u32 spi_setup1;
> +u32 spi_setup2;
> +u32 spi_setup3;
> +u32 spi_switch;
> +u32 spi_data1;
> +u32 spi_data2;
> +u32 spi_data3;
Please add tab space.
> +};
> +
> +struct qspi_slave {
> + struct spi_slave slave;
> + struct qspi_regs *base;
> + unsigned int mode;
> + u32 cmd;
> + u32 dc;
> +};
> +
-- TAG+
> +#define QSPI_TIMEOUT 200
> +
> +#define QSPI_FCLK 19200
> +
> +/* Clock Control */
> +#define QSPI_CLK_EN(1 << 31)
> +#define QSPI_CLK_DIV_MAX 0x
> +
> +/* Command */
> +#define QSPI_EN_CS(n) (n << 28)
> +#define QSPI_WLEN(n) ((n-1) << 19)
> +#define QSPI_3_PIN (1 << 18)
> +#define QSPI_RD_SNGL (1 << 16)
> +#define QSPI_WR_SNGL (2 << 16)
> +#define QSPI_INVAL (4 << 16)
> +#define QSPI_RD_QUAD (7 << 16)
> +
> +/* Device Control */
> +#define QSPI_DD(m, n) (m << (3 + n*8))
> +#define QSPI_CKPHA(n) (1 << (2 + n*8))
> +#define QSPI_CSPOL(n) (1 << (1 + n*8))
> +#define QSPI_CKPOL(n) (1 << (n*8))
> +
> +/* Status */
> +#define QSPI_WC(1 << 1)
> +#define QSPI_BUSY (1 << 0)
> +#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
> +#define QSPI_XFER_DONE QSPI_WC
> +
> +#define MM_SWITCH 0x01
> +#define MEM_CS 0x100
> +#define MEM_CS_UNSELECT0xf0ff
> +#define MMAP_START_ADDR0x5c00
> +#define CORE_CTRL_IO 0x4a002558
> +
> +#define QSPI_CMD_READ (0x3 << 0)
> +#define QSPI_CMD_READ_QUAD (0x6b << 0)
> +#define QSPI_CMD_READ_FAST (0x0b << 0)
> +#define QSPI_SETUP0_NUM_A_BYTES(0x2 << 8)
> +#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0 << 10)
> +#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
> +#define QSPI_SETUP0_READ_NORMAL(0x0 << 12)
> +#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
> +#define QSPI_CMD_WRITE (0x2 << 16)
> +#define QSPI_NUM_DUMMY_BITS(0x0 << 24)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
> +
> +static inline struct qspi_slave *to_qspi_slave(struct spi_slave *slave)
> +{
> + return container_of(slave, struct qspi_slave, slave);
> +}
> +static inline struct qspi_regs *get_qspi_bus(int dev)
> +{
> + if (!dev)
> + return (struct qspi_regs *)QSPI_BASE;
> + else
> + return NULL;
> +}
Is this function really required, how many bus controller you have?
> +
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> + return 1;
> +}
> +
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> + /* CS handled in xfer */
> + return;
> +}
> +
> +void spi_cs_deactivat
[U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
---
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328 +
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ *Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 << 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n << 28)
+#define QSPI_WLEN(n) ((n-1) << 19)
+#define QSPI_3_PIN (1 << 18)
+#define QSPI_RD_SNGL (1 << 16)
+#define QSPI_WR_SNGL (2 << 16)
+#define QSPI_INVAL (4 << 16)
+#define QSPI_RD_QUAD (7 << 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m << (3 + n*8))
+#define QSPI_CKPHA(n) (1 << (2 + n*8))
+#define QSPI_CSPOL(n) (1 << (1 + n*8))
+#define QSPI_CKPOL(n) (1 << (n*8))
+
+/* Status */
+#define QSPI_WC(1 << 1)
+#define QSPI_BUSY (1 << 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3 << 0)
+#define QSPI_CMD_READ_QUAD (0x6b << 0)
+#define QSPI_CMD_READ_FAST (0x0b << 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2 << 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0 << 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0 << 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
+#define QSPI_CMD_WRITE (0x2 << 16)
+#define QSPI_NUM_DUMMY_BITS(0x0 << 24)
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline struct qspi_regs *get_qspi_bus(int dev)
+{
+ if (!dev)
+ return (struct qspi_regs *)QSPI_BASE;
+ else
+ return NULL;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+void spi_set_up_spi_register(struct qspi_slave *qslave)
+{
+ u32 memval = 0;
+ struct spi_slave *slave = &qslave->slave;
+
+ slave->memory_map = (void *)MMAP_START_ADDR;
+
+ memval |= (QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL |
+ QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS);
+
+ writel(memval, &qslave->base->spi_setup0);
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ struct qspi_slave *qslave = to_qspi_slave(slave);
+
+ uint clk_div;
+
+ if (!hz)
+ clk_div = 0;
+ els
