Re: [U-Boot] [UNTESTED PATCH] ARM: orion5x: fix use of callee-saved registers in lowloevel_init

2018-05-07 Thread Chris Packham 
On Mon, May 7, 2018 at 10:11 PM Mans Rullgard  wrote:

> The lowlevel_init function uses r4 and r6 without preserving their
> values as required by the AAPCS.  Use r0 and r2 instead as these
> are call-clobbered.

> Signed-off-by: Mans Rullgard 
> ---
>   arch/arm/mach-orion5x/lowlevel_init.S | 168 +-
>   1 file changed, 84 insertions(+), 84 deletions(-)

> diff --git a/arch/arm/mach-orion5x/lowlevel_init.S
b/arch/arm/mach-orion5x/lowlevel_init.S
> index 3f38f36ff294..a4e113601013 100644
> --- a/arch/arm/mach-orion5x/lowlevel_init.S
> +++ b/arch/arm/mach-orion5x/lowlevel_init.S
> @@ -72,67 +72,67 @@ lowlevel_init:

>   #ifdef CONFIG_SPL_BUILD

> -   /* Use 'r4 as the base for internal register accesses */
> -   ldr r4, =ORION5X_REGS_PHY_BASE
> +   /* Use 'r2 as the base for internal register accesses */
> +   ldr r2, =ORION5X_REGS_PHY_BASE

>  /* move internal registers from the default 0xD000
>   * to their intended location, defined by SoC */
>  ldr r3, =0xD000
>  add r3, r3, #0x2
> -   str r4, [r3, #0x80]
> +   str r2, [r3, #0x80]

>  /* Use R3 as the base for DRAM registers */
> -   add r3, r4, #0x01000
> +   add r3, r2, #0x01000

>  /*DDR SDRAM Initialization Control */
> -   ldr r6, =0x0001
> -   str r6, [r3, #0x480]
> +   ldr r0, =0x0001
> +   str r0, [r3, #0x480]

>  /* Use R3 as the base for PCI registers */
> -   add r3, r4, #0x31000
> +   add r3, r2, #0x31000

>  /* Disable arbiter */
> -   ldr r6, =0x0030
> -   str r6, [r3, #0xd00]
> +   ldr r0, =0x0030
> +   str r0, [r3, #0xd00]

>  /* Use R3 as the base for DRAM registers */
> -   add r3, r4, #0x01000
> +   add r3, r2, #0x01000

>  /* set all dram windows to 0 */
> -   mov r6, #0
> -   str r6, [r3, #0x504]
> -   str r6, [r3, #0x50C]
> -   str r6, [r3, #0x514]
> -   str r6, [r3, #0x51C]
> +   mov r0, #0
> +   str r0, [r3, #0x504]
> +   str r0, [r3, #0x50C]
> +   str r0, [r3, #0x514]
> +   str r0, [r3, #0x51C]

>  /* 1) Configure SDRAM  */
> -   ldr r6, =SDRAM_CONFIG
> -   str r6, [r3, #0x400]
> +   ldr r0, =SDRAM_CONFIG
> +   str r0, [r3, #0x400]

>  /* 2) Set SDRAM Control reg */
> -   ldr r6, =SDRAM_CONTROL
> -   str r6, [r3, #0x404]
> +   ldr r0, =SDRAM_CONTROL
> +   str r0, [r3, #0x404]

>  /* 3) Write SDRAM address control register */
> -   ldr r6, =SDRAM_ADDR_CTRL
> -   str r6, [r3, #0x410]
> +   ldr r0, =SDRAM_ADDR_CTRL
> +   str r0, [r3, #0x410]

>  /* 4) Write SDRAM bank 0 size register */
> -   ldr r6, =SDRAM_BANK0_SIZE
> -   str r6, [r3, #0x504]
> +   ldr r0, =SDRAM_BANK0_SIZE
> +   str r0, [r3, #0x504]
>  /* keep other banks disabled */

>  /* 5) Write SDRAM open pages control register */
> -   ldr r6, =SDRAM_OPEN_PAGE_EN
> -   str r6, [r3, #0x414]
> +   ldr r0, =SDRAM_OPEN_PAGE_EN
> +   str r0, [r3, #0x414]

>  /* 6) Write SDRAM timing Low register */
> -   ldr r6, =SDRAM_TIME_CTRL_LOW
> -   str r6, [r3, #0x408]
> +   ldr r0, =SDRAM_TIME_CTRL_LOW
> +   str r0, [r3, #0x408]

>  /* 7) Write SDRAM timing High register */
> -   ldr r6, =SDRAM_TIME_CTRL_HI
> -   str r6, [r3, #0x40C]
> +   ldr r0, =SDRAM_TIME_CTRL_HI
> +   str r0, [r3, #0x40C]

>  /* 8) Write SDRAM mode register */
>  /* The CPU must not attempt to change the SDRAM Mode register
setting */
> @@ -143,73 +143,73 @@ lowlevel_init:
>  /* and then sets SDRAM Mode register to its new value.
  */

>  /* 8.1 write 'nop' to SDRAM operation */
> -   ldr r6, =SDRAM_OP_NOP
> -   str r6, [r3, #0x418]
> +   ldr r0, =SDRAM_OP_NOP
> +   str r0, [r3, #0x418]

>  /* 8.2 poll SDRAM operation until back in 'normal' mode.  */
>   1:
> -   ldr r6, [r3, #0x418]
> -   cmp r6, #0
> +   ldr r0, [r3, #0x418]
> +   cmp r0, #0
>  bne 1b

>  /* 8.3 Now its safe to write new value to SDRAM Mode register
 */
> -   ldr r6, =SDRAM_MODE
> -   str r6, [r3, #0x41C]
> +   ldr r0, =SDRAM_MODE
> +   str r0, [r3, #0x41C]

>  /* 8.4 Set new mode */
> -   ldr r6, =SDRAM_OP_SETMODE
> -   str r6, [r3, #0x418]
> +   ldr r0, =SDRAM_OP_SETMODE
> +   str r0, [r3, #0x418]

>  /* 8.5 poll SDRAM operation until back in 'normal' mode.  */
>   2:
> -   ldr r6, [r3, #0x418]
> -   cmp r6, #0
> +   ldr r0, [r3,

[U-Boot] [UNTESTED PATCH] ARM: orion5x: fix use of callee-saved registers in lowloevel_init

2018-05-07 Thread Mans Rullgard 
The lowlevel_init function uses r4 and r6 without preserving their
values as required by the AAPCS.  Use r0 and r2 instead as these
are call-clobbered.

Signed-off-by: Mans Rullgard 
---
 arch/arm/mach-orion5x/lowlevel_init.S | 168 +-
 1 file changed, 84 insertions(+), 84 deletions(-)

diff --git a/arch/arm/mach-orion5x/lowlevel_init.S 
b/arch/arm/mach-orion5x/lowlevel_init.S
index 3f38f36ff294..a4e113601013 100644
--- a/arch/arm/mach-orion5x/lowlevel_init.S
+++ b/arch/arm/mach-orion5x/lowlevel_init.S
@@ -72,67 +72,67 @@ lowlevel_init:
 
 #ifdef CONFIG_SPL_BUILD
 
-   /* Use 'r4 as the base for internal register accesses */
-   ldr r4, =ORION5X_REGS_PHY_BASE
+   /* Use 'r2 as the base for internal register accesses */
+   ldr r2, =ORION5X_REGS_PHY_BASE
 
/* move internal registers from the default 0xD000
 * to their intended location, defined by SoC */
ldr r3, =0xD000
add r3, r3, #0x2
-   str r4, [r3, #0x80]
+   str r2, [r3, #0x80]
 
/* Use R3 as the base for DRAM registers */
-   add r3, r4, #0x01000
+   add r3, r2, #0x01000
 
/*DDR SDRAM Initialization Control */
-   ldr r6, =0x0001
-   str r6, [r3, #0x480]
+   ldr r0, =0x0001
+   str r0, [r3, #0x480]
 
/* Use R3 as the base for PCI registers */
-   add r3, r4, #0x31000
+   add r3, r2, #0x31000
 
/* Disable arbiter */
-   ldr r6, =0x0030
-   str r6, [r3, #0xd00]
+   ldr r0, =0x0030
+   str r0, [r3, #0xd00]
 
/* Use R3 as the base for DRAM registers */
-   add r3, r4, #0x01000
+   add r3, r2, #0x01000
 
/* set all dram windows to 0 */
-   mov r6, #0
-   str r6, [r3, #0x504]
-   str r6, [r3, #0x50C]
-   str r6, [r3, #0x514]
-   str r6, [r3, #0x51C]
+   mov r0, #0
+   str r0, [r3, #0x504]
+   str r0, [r3, #0x50C]
+   str r0, [r3, #0x514]
+   str r0, [r3, #0x51C]
 
/* 1) Configure SDRAM  */
-   ldr r6, =SDRAM_CONFIG
-   str r6, [r3, #0x400]
+   ldr r0, =SDRAM_CONFIG
+   str r0, [r3, #0x400]
 
/* 2) Set SDRAM Control reg */
-   ldr r6, =SDRAM_CONTROL
-   str r6, [r3, #0x404]
+   ldr r0, =SDRAM_CONTROL
+   str r0, [r3, #0x404]
 
/* 3) Write SDRAM address control register */
-   ldr r6, =SDRAM_ADDR_CTRL
-   str r6, [r3, #0x410]
+   ldr r0, =SDRAM_ADDR_CTRL
+   str r0, [r3, #0x410]
 
/* 4) Write SDRAM bank 0 size register */
-   ldr r6, =SDRAM_BANK0_SIZE
-   str r6, [r3, #0x504]
+   ldr r0, =SDRAM_BANK0_SIZE
+   str r0, [r3, #0x504]
/* keep other banks disabled */
 
/* 5) Write SDRAM open pages control register */
-   ldr r6, =SDRAM_OPEN_PAGE_EN
-   str r6, [r3, #0x414]
+   ldr r0, =SDRAM_OPEN_PAGE_EN
+   str r0, [r3, #0x414]
 
/* 6) Write SDRAM timing Low register */
-   ldr r6, =SDRAM_TIME_CTRL_LOW
-   str r6, [r3, #0x408]
+   ldr r0, =SDRAM_TIME_CTRL_LOW
+   str r0, [r3, #0x408]
 
/* 7) Write SDRAM timing High register */
-   ldr r6, =SDRAM_TIME_CTRL_HI
-   str r6, [r3, #0x40C]
+   ldr r0, =SDRAM_TIME_CTRL_HI
+   str r0, [r3, #0x40C]
 
/* 8) Write SDRAM mode register */
/* The CPU must not attempt to change the SDRAM Mode register setting */
@@ -143,73 +143,73 @@ lowlevel_init:
/* and then sets SDRAM Mode register to its new value.*/
 
/* 8.1 write 'nop' to SDRAM operation */
-   ldr r6, =SDRAM_OP_NOP
-   str r6, [r3, #0x418]
+   ldr r0, =SDRAM_OP_NOP
+   str r0, [r3, #0x418]
 
/* 8.2 poll SDRAM operation until back in 'normal' mode.  */
 1:
-   ldr r6, [r3, #0x418]
-   cmp r6, #0
+   ldr r0, [r3, #0x418]
+   cmp r0, #0
bne 1b
 
/* 8.3 Now its safe to write new value to SDRAM Mode register */
-   ldr r6, =SDRAM_MODE
-   str r6, [r3, #0x41C]
+   ldr r0, =SDRAM_MODE
+   str r0, [r3, #0x41C]
 
/* 8.4 Set new mode */
-   ldr r6, =SDRAM_OP_SETMODE
-   str r6, [r3, #0x418]
+   ldr r0, =SDRAM_OP_SETMODE
+   str r0, [r3, #0x418]
 
/* 8.5 poll SDRAM operation until back in 'normal' mode.  */
 2:
-   ldr r6, [r3, #0x418]
-   cmp r6, #0
+   ldr r0, [r3, #0x418]
+   cmp r0, #0
bne 2b
 
/* DDR SDRAM Address/Control Pads Calibration */
-   ldr r6, [r3, #0x4C0]
+   ldr r0, [r3, #0x4C0]
 
/* Set Bit [31] to make the register writable   */
-   orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
-   str