From: Zhong Hongbo bocui...@gmail.com
Adopt the new SPL framework to implement the SPL booting of
the nand flash for S3C6400.
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V3:
- None.
Change for V2:
- seprate some code.
---
arch/arm/cpu/arm1176/start.S| 16 +---
board/samsung/smdk6400/Makefile | 29 +-
board/samsung/smdk6400/lowlevel_init.S | 22 ++--
board/samsung/smdk6400/smdk6400_nand_spl.c | 61 ++--
board/samsung/smdk6400/tools/mksmdk6400_image.c | 117 +++
drivers/mtd/nand/s3c64xx.c |4 +-
include/configs/smdk6400.h | 21 +++--
7 files changed, 221 insertions(+), 49 deletions(-)
create mode 100644 board/samsung/smdk6400/tools/mksmdk6400_image.c
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index d613641..761b7fe 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -51,7 +51,7 @@
.globl _start
_start: b reset
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -164,7 +164,7 @@ cpu_init_crit:
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
* flush v4 I/D caches
*/
@@ -357,21 +357,14 @@ clbss_l:cmp r0, r1 /* clear
loop... */
add r0, r0, #4
b clbss_l
clbss_e:
-#ifndef CONFIG_NAND_SPL
bl coloured_LED_init
bl red_led_on
#endif
-#endif
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
-#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
-
-_nand_boot: .word nand_boot
-#else
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
@@ -384,7 +377,6 @@ _nand_boot: .word nand_boot
_board_init_r_ofs:
.word board_init_r - _start
-#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
@@ -398,7 +390,7 @@ _mmu_table_base:
.word mmu_table
#endif
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
* we assume that cache operation is done before. (eg. cleanup_before_linux())
* actually, we don't need to do anything about cache if not use d-cache in
@@ -576,4 +568,4 @@ fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile
index 645c8e2..f7fa667 100644
--- a/board/samsung/smdk6400/Makefile
+++ b/board/samsung/smdk6400/Makefile
@@ -28,15 +28,34 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
+ifndef CONFIG_SPL_BUILD
COBJS-y:= smdk6400.o
+endif
+
SOBJS := lowlevel_init.o mem_init.o
-SRCS:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+ifdef CONFIG_SPL_BUILD
+COBJS-y += smdk6400_nand_spl.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+
+ALL:= $(obj).depend $(LIB)
+
+ifdef CONFIG_SPL_BUILD
+ALL+= $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
+all: $(ALL)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
-$(LIB):$(obj).depend $(SOBJS) $(OBJS)
- $(call cmd_link_o_target, $(SOBJS) $(OBJS))
+ifdef CONFIG_SPL_BUILD
+$(OBJTREE)/tools/mk$(BOARD)spl:tools/mksmdk6400_image.c
+ $(HOSTCC) tools/mksmdk6400_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+endif
#
diff --git a/board/samsung/smdk6400/lowlevel_init.S
b/board/samsung/smdk6400/lowlevel_init.S
index 45887f3..93172e7 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -84,18 +84,12 @@ lowlevel_init:
str r3, [r0, #oVECTADDR]
str r3, [r1, #oVECTADDR]
+#ifdef CONFIG_SPL_BUILD
/* init system clock */
- bl system_clock_init
+ bl system_clock_init
-#ifndef CONFIG_NAND_SPL
- /* for UART */
- bl uart_asm_init
-#endif
-
-#ifdef CONFIG_BOOT_NAND
/* simple init for NAND */
- bl nand_asm_init
-#endif
+ bl nand_asm_init
/* Memory subsystem address 0x7e00f120 */
ldr r0, =ELFIN_MEM_SYS_CFG
@@ -105,6 +99,12 @@ lowlevel_init:
str r1, [r0]
bl mem_ctrl_asm_init
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+ /* for UART */
+ bl uart_asm_init
+#endif
/* Wakeup support. Don't know if it's going to be used, untested. */
ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
@@ -244,7 +244,7 @@ wait_for_async:
