Re: [U-Boot] [uboot] [PATCH v5 4/7] net: phy: ti: Allow the driver to be more configurable

[Mugunthan V N]

On Monday 11 April 2016 05:48 PM, Dan Murphy wrote:
> Not all devices use the same internal delay or fifo depth.
> Add the ability to set the internal delay for rx or tx and the
> fifo depth via the devicetree.  If the value is not set in the
> devicetree then set the delay to the default.
> 
> If devicetree is not used then use the default defines within the
> driver.
> 
> Signed-off-by: Dan Murphy 
> ---
> 
> v5 - Removed extra space and renamed the bindings per the bindings document - 
> https://patchwork.ozlabs.org/patch/608087/
> 
>  drivers/net/phy/ti.c | 85 
> +---
>  1 file changed, 75 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
> index 937426b..b8f3ebd 100644
> --- a/drivers/net/phy/ti.c
> +++ b/drivers/net/phy/ti.c
> @@ -6,6 +6,14 @@
>   */
>  #include 
>  #include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
>  
>  /* TI DP83867 */
>  #define DP83867_DEVADDR  0x1f
> @@ -71,6 +79,17 @@
>  #define MII_MMD_CTRL_INCR_RDWT   0x8000 /* post increment on reads & 
> writes */
>  #define MII_MMD_CTRL_INCR_ON_WT  0xC000 /* post increment on writes only 
> */
>  
> +/* User setting - can be taken from DTS */
> +#define DEFAULT_RX_ID_DELAY  DP83867_RGMIIDCTL_2_25_NS
> +#define DEFAULT_TX_ID_DELAY  DP83867_RGMIIDCTL_2_75_NS
> +#define DEFAULT_FIFO_DEPTH   DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
> +
> +struct dp83867_private {
> + int rx_id_delay;
> + int tx_id_delay;
> + int fifo_depth;
> +};
> +
>  /**
>   * phy_read_mmd_indirect - reads data from the MMD registers
>   * @phydev: The PHY device bus
> @@ -148,16 +167,58 @@ static inline bool phy_interface_is_rgmii(struct 
> phy_device *phydev)
>   phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
>  }
>  
> -/* User setting - can be taken from DTS */
> -#define RX_ID_DELAY  8
> -#define TX_ID_DELAY  0xa
> -#define FIFO_DEPTH   1
> +#if defined(CONFIG_DM_ETH)
> +/**
> + * dp83867_data_init - Convenience function for setting PHY specific data
> + *
> + * @phydev: the phy_device struct
> + */
> +static int dp83867_of_init(struct phy_device *phydev)
> +{
> + struct dp83867_private *dp83867 = phydev->priv;
> + struct udevice *dev = phydev->dev;
> +
> + dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,rx-internal-delay", -1);
> +
> + dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,tx-internal-delay", -1);
> +
> + dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,fifo-depth", -1);
> +
> + return 0;
> +}
> +#else
> +static int dp83867_of_init(struct phy_device *phydev)
> +{
> + dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
> + dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
> + dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
> +
> + return 0;
> +}

Below statement missing:
struct dp83867_private *dp83867 = phydev->priv;

Build error:

drivers/net/phy/ti.c: In function ‘dp83867_of_init’:
drivers/net/phy/ti.c:184:2: error: ‘dp83867’ undeclared (first use in
this function)
  dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
  ^
drivers/net/phy/ti.c:184:2: note: each undeclared identifier is reported
only once for each function it appears in
scripts/Makefile.build:280: recipe for target 'drivers/net/phy/ti.o' failed


> +#endif
>  
>  static int dp83867_config(struct phy_device *phydev)
>  {
> + struct dp83867_private *dp83867;
>   unsigned int val, delay, cfg2;
>   int ret;
>  
> + if (!phydev->priv) {
> + dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
> + if (!dp83867)
> + return -ENOMEM;
> +
> + phydev->priv = dp83867;
> + ret = dp83867_of_init(phydev);
> + if (ret)
> + goto err_out;
> + } else {
> + dp83867 = (struct dp83867_private *)phydev->priv;
> + }
> +
>   /* Restart the PHY.  */
>   val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
>   phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
> @@ -166,9 +227,9 @@ static int dp83867_config(struct phy_device *phydev)
>   if (phy_interface_is_rgmii(phydev)) {
>   ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
>   (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
> - (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
> + (dp83867->fifo_depth << 
> DP83867_PHYCR_FIFO_DEPTH_SHIFT));
>   if (ret)
> - return ret;
> + goto err_out;
>   } else {
>   phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
> (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
> @@ -189,8 +250,8 @@ static int 

Re: [U-Boot] [uboot] [PATCH v5 4/7] net: phy: ti: Allow the driver to be more configurable

[Dan Murphy]

Adding Joe

On 04/11/2016 07:18 AM, Dan Murphy wrote:
> Not all devices use the same internal delay or fifo depth.
> Add the ability to set the internal delay for rx or tx and the
> fifo depth via the devicetree.  If the value is not set in the
> devicetree then set the delay to the default.
>
> If devicetree is not used then use the default defines within the
> driver.
>
> Signed-off-by: Dan Murphy 
> ---
>
> v5 - Removed extra space and renamed the bindings per the bindings document - 
> https://patchwork.ozlabs.org/patch/608087/
>
>  drivers/net/phy/ti.c | 85 
> +---
>  1 file changed, 75 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
> index 937426b..b8f3ebd 100644
> --- a/drivers/net/phy/ti.c
> +++ b/drivers/net/phy/ti.c
> @@ -6,6 +6,14 @@
>   */
>  #include 
>  #include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
>  
>  /* TI DP83867 */
>  #define DP83867_DEVADDR  0x1f
> @@ -71,6 +79,17 @@
>  #define MII_MMD_CTRL_INCR_RDWT   0x8000 /* post increment on reads & 
> writes */
>  #define MII_MMD_CTRL_INCR_ON_WT  0xC000 /* post increment on writes only 
> */
>  
> +/* User setting - can be taken from DTS */
> +#define DEFAULT_RX_ID_DELAY  DP83867_RGMIIDCTL_2_25_NS
> +#define DEFAULT_TX_ID_DELAY  DP83867_RGMIIDCTL_2_75_NS
> +#define DEFAULT_FIFO_DEPTH   DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
> +
> +struct dp83867_private {
> + int rx_id_delay;
> + int tx_id_delay;
> + int fifo_depth;
> +};
> +
>  /**
>   * phy_read_mmd_indirect - reads data from the MMD registers
>   * @phydev: The PHY device bus
> @@ -148,16 +167,58 @@ static inline bool phy_interface_is_rgmii(struct 
> phy_device *phydev)
>   phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
>  }
>  
> -/* User setting - can be taken from DTS */
> -#define RX_ID_DELAY  8
> -#define TX_ID_DELAY  0xa
> -#define FIFO_DEPTH   1
> +#if defined(CONFIG_DM_ETH)
> +/**
> + * dp83867_data_init - Convenience function for setting PHY specific data
> + *
> + * @phydev: the phy_device struct
> + */
> +static int dp83867_of_init(struct phy_device *phydev)
> +{
> + struct dp83867_private *dp83867 = phydev->priv;
> + struct udevice *dev = phydev->dev;
> +
> + dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,rx-internal-delay", -1);
> +
> + dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,tx-internal-delay", -1);
> +
> + dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,fifo-depth", -1);
> +
> + return 0;
> +}
> +#else
> +static int dp83867_of_init(struct phy_device *phydev)
> +{
> + dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
> + dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
> + dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
> +
> + return 0;
> +}
> +#endif
>  
>  static int dp83867_config(struct phy_device *phydev)
>  {
> + struct dp83867_private *dp83867;
>   unsigned int val, delay, cfg2;
>   int ret;
>  
> + if (!phydev->priv) {
> + dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
> + if (!dp83867)
> + return -ENOMEM;
> +
> + phydev->priv = dp83867;
> + ret = dp83867_of_init(phydev);
> + if (ret)
> + goto err_out;
> + } else {
> + dp83867 = (struct dp83867_private *)phydev->priv;
> + }
> +
>   /* Restart the PHY.  */
>   val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
>   phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
> @@ -166,9 +227,9 @@ static int dp83867_config(struct phy_device *phydev)
>   if (phy_interface_is_rgmii(phydev)) {
>   ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
>   (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
> - (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
> + (dp83867->fifo_depth << 
> DP83867_PHYCR_FIFO_DEPTH_SHIFT));
>   if (ret)
> - return ret;
> + goto err_out;
>   } else {
>   phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
> (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
> @@ -189,8 +250,8 @@ static int dp83867_config(struct phy_device *phydev)
> DP83867_PHYCTRL_SGMIIEN |
> (DP83867_MDI_CROSSOVER_MDIX <<
> DP83867_MDI_CROSSOVER) |
> -   (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
> -   (FIFO_DEPTH  << DP83867_PHYCTRL_TXFIFO_SHIFT));
> +   (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) 
> |
> +   (dp83867->fifo_depth << 
> 

Re: [U-Boot] [uboot] [PATCH v5 4/7] net: phy: ti: Allow the driver to be more configurable

[Michal Simek]

On 11.4.2016 14:18, Dan Murphy wrote:
> Not all devices use the same internal delay or fifo depth.
> Add the ability to set the internal delay for rx or tx and the
> fifo depth via the devicetree.  If the value is not set in the
> devicetree then set the delay to the default.
> 
> If devicetree is not used then use the default defines within the
> driver.
> 
> Signed-off-by: Dan Murphy 
> ---
> 
> v5 - Removed extra space and renamed the bindings per the bindings document - 
> https://patchwork.ozlabs.org/patch/608087/
> 
>  drivers/net/phy/ti.c | 85 
> +---
>  1 file changed, 75 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
> index 937426b..b8f3ebd 100644
> --- a/drivers/net/phy/ti.c
> +++ b/drivers/net/phy/ti.c
> @@ -6,6 +6,14 @@
>   */
>  #include 
>  #include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
>  
>  /* TI DP83867 */
>  #define DP83867_DEVADDR  0x1f
> @@ -71,6 +79,17 @@
>  #define MII_MMD_CTRL_INCR_RDWT   0x8000 /* post increment on reads & 
> writes */
>  #define MII_MMD_CTRL_INCR_ON_WT  0xC000 /* post increment on writes only 
> */
>  
> +/* User setting - can be taken from DTS */
> +#define DEFAULT_RX_ID_DELAY  DP83867_RGMIIDCTL_2_25_NS
> +#define DEFAULT_TX_ID_DELAY  DP83867_RGMIIDCTL_2_75_NS
> +#define DEFAULT_FIFO_DEPTH   DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
> +
> +struct dp83867_private {
> + int rx_id_delay;
> + int tx_id_delay;
> + int fifo_depth;
> +};
> +
>  /**
>   * phy_read_mmd_indirect - reads data from the MMD registers
>   * @phydev: The PHY device bus
> @@ -148,16 +167,58 @@ static inline bool phy_interface_is_rgmii(struct 
> phy_device *phydev)
>   phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
>  }
>  
> -/* User setting - can be taken from DTS */
> -#define RX_ID_DELAY  8
> -#define TX_ID_DELAY  0xa
> -#define FIFO_DEPTH   1
> +#if defined(CONFIG_DM_ETH)
> +/**
> + * dp83867_data_init - Convenience function for setting PHY specific data
> + *
> + * @phydev: the phy_device struct
> + */
> +static int dp83867_of_init(struct phy_device *phydev)
> +{
> + struct dp83867_private *dp83867 = phydev->priv;
> + struct udevice *dev = phydev->dev;
> +
> + dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,rx-internal-delay", -1);
> +
> + dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,tx-internal-delay", -1);
> +
> + dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
> +  "ti,fifo-depth", -1);
> +
> + return 0;
> +}
> +#else
> +static int dp83867_of_init(struct phy_device *phydev)
> +{
> + dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
> + dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
> + dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
> +
> + return 0;
> +}
> +#endif
>  
>  static int dp83867_config(struct phy_device *phydev)
>  {
> + struct dp83867_private *dp83867;
>   unsigned int val, delay, cfg2;
>   int ret;
>  
> + if (!phydev->priv) {
> + dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
> + if (!dp83867)
> + return -ENOMEM;
> +
> + phydev->priv = dp83867;
> + ret = dp83867_of_init(phydev);
> + if (ret)
> + goto err_out;
> + } else {
> + dp83867 = (struct dp83867_private *)phydev->priv;
> + }
> +
>   /* Restart the PHY.  */
>   val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
>   phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
> @@ -166,9 +227,9 @@ static int dp83867_config(struct phy_device *phydev)
>   if (phy_interface_is_rgmii(phydev)) {
>   ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
>   (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
> - (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
> + (dp83867->fifo_depth << 
> DP83867_PHYCR_FIFO_DEPTH_SHIFT));
>   if (ret)
> - return ret;
> + goto err_out;
>   } else {
>   phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
> (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
> @@ -189,8 +250,8 @@ static int dp83867_config(struct phy_device *phydev)
> DP83867_PHYCTRL_SGMIIEN |
> (DP83867_MDI_CROSSOVER_MDIX <<
> DP83867_MDI_CROSSOVER) |
> -   (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
> -   (FIFO_DEPTH  << DP83867_PHYCTRL_TXFIFO_SHIFT));
> +   (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) 
> |
> +   (dp83867->fifo_depth << 
> 

[U-Boot] [uboot] [PATCH v5 4/7] net: phy: ti: Allow the driver to be more configurable

[Dan Murphy]

Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree.  If the value is not set in the
devicetree then set the delay to the default.

If devicetree is not used then use the default defines within the
driver.

Signed-off-by: Dan Murphy 
---

v5 - Removed extra space and renamed the bindings per the bindings document - 
https://patchwork.ozlabs.org/patch/608087/

 drivers/net/phy/ti.c | 85 +---
 1 file changed, 75 insertions(+), 10 deletions(-)

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 937426b..b8f3ebd 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -6,6 +6,14 @@
  */
 #include 
 #include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* TI DP83867 */
 #define DP83867_DEVADDR0x1f
@@ -71,6 +79,17 @@
 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
 #define MII_MMD_CTRL_INCR_ON_WT0xC000 /* post increment on writes only 
*/
 
+/* User setting - can be taken from DTS */
+#define DEFAULT_RX_ID_DELAYDP83867_RGMIIDCTL_2_25_NS
+#define DEFAULT_TX_ID_DELAYDP83867_RGMIIDCTL_2_75_NS
+#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
+
+struct dp83867_private {
+   int rx_id_delay;
+   int tx_id_delay;
+   int fifo_depth;
+};
+
 /**
  * phy_read_mmd_indirect - reads data from the MMD registers
  * @phydev: The PHY device bus
@@ -148,16 +167,58 @@ static inline bool phy_interface_is_rgmii(struct 
phy_device *phydev)
phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 }
 
-/* User setting - can be taken from DTS */
-#define RX_ID_DELAY8
-#define TX_ID_DELAY0xa
-#define FIFO_DEPTH 1
+#if defined(CONFIG_DM_ETH)
+/**
+ * dp83867_data_init - Convenience function for setting PHY specific data
+ *
+ * @phydev: the phy_device struct
+ */
+static int dp83867_of_init(struct phy_device *phydev)
+{
+   struct dp83867_private *dp83867 = phydev->priv;
+   struct udevice *dev = phydev->dev;
+
+   dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+"ti,rx-internal-delay", -1);
+
+   dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+"ti,tx-internal-delay", -1);
+
+   dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+"ti,fifo-depth", -1);
+
+   return 0;
+}
+#else
+static int dp83867_of_init(struct phy_device *phydev)
+{
+   dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
+   dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
+   dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+
+   return 0;
+}
+#endif
 
 static int dp83867_config(struct phy_device *phydev)
 {
+   struct dp83867_private *dp83867;
unsigned int val, delay, cfg2;
int ret;
 
+   if (!phydev->priv) {
+   dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+   if (!dp83867)
+   return -ENOMEM;
+
+   phydev->priv = dp83867;
+   ret = dp83867_of_init(phydev);
+   if (ret)
+   goto err_out;
+   } else {
+   dp83867 = (struct dp83867_private *)phydev->priv;
+   }
+
/* Restart the PHY.  */
val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
@@ -166,9 +227,9 @@ static int dp83867_config(struct phy_device *phydev)
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
-   (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+   (dp83867->fifo_depth << 
DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
-   return ret;
+   goto err_out;
} else {
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
@@ -189,8 +250,8 @@ static int dp83867_config(struct phy_device *phydev)
  DP83867_PHYCTRL_SGMIIEN |
  (DP83867_MDI_CROSSOVER_MDIX <<
  DP83867_MDI_CROSSOVER) |
- (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
- (FIFO_DEPTH  << DP83867_PHYCTRL_TXFIFO_SHIFT));
+ (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) 
|
+ (dp83867->fifo_depth << 
DP83867_PHYCTRL_TXFIFO_SHIFT));
phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
}
 
@@ -212,8 +273,8 @@ static int dp83867_config(struct phy_device *phydev)