Re: [U-Boot] [PATCH v3] arm: zynq: add support for the zybo z7 board
On 24.7.2018 17:31, Luis Araneda wrote:
> The board is manufactured by Digilent
> Main features:
> - Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20)
> - RAM: 1 GB DDR3L
> - FLASH: 16 MB QSPI
> - 1 Gbps Ethernet
> - USB 2.0
> - microSD slot
> - Pcam camera connector
> - HDMI Tx and Rx
> - Audio codec: stereo out, stereo in, mic
> - 5 (Z7-10) or 6 (Z7-20) Pmod ports
> - 6 push-buttons, 4 switches, 5 LEDs
> - 1 (Z7-10) or 2 (Z7-20) RGB LEDs
>
> Signed-off-by: Luis Araneda
> ---
>
> This patch adds support for the Digilent Zybo Z7 board
>
> The only thing that I tested and is not working yet, is reading the
> MAC address from the OTP region of the SPI flash memory, but I'm trying
> to find a solution
>
> Changes from v2:
> - Removed silicon version 2_0 and 1_0 from ps7_init_gpl.c
>
> Changes from v1:
> - Rebased on u-boot/master
> - Removed comments and indented ps7_init_gpl.c
> - Removed CONFIG_DISPLAY from defconfig
> - Replaced the cadence I2C driver by zynq_i2c
> - Squashed the patches as they are less than 100kB now
> ---
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/zynq-zybo-z7.dts | 81 +
> board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c | 297 ++
> configs/zynq_zybo_z7_defconfig| 68
> 4 files changed, 448 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/zynq-zybo-z7.dts
> create mode 100644 board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
> create mode 100644 configs/zynq_zybo_z7_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 09adf5eab1..07d8729104 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -149,7 +149,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
> zynq-zc770-xm013.dtb \
> zynq-zed.dtb \
> zynq-zturn.dtb \
> - zynq-zybo.dtb
> + zynq-zybo.dtb \
> + zynq-zybo-z7.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += \
> zynqmp-mini-emmc0.dtb \
> zynqmp-mini-emmc1.dtb \
> diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts
> new file mode 100644
> index 00..3f8a3bfa0f
> --- /dev/null
> +++ b/arch/arm/dts/zynq-zybo-z7.dts
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2011 - 2015 Xilinx
> + * Copyright (C) 2012 National Instruments Corp.
> + */
> +/dts-v1/;
> +#include "zynq-7000.dtsi"
> +#include
> +
> +/ {
> + model = "Digilent Zybo Z7 board";
> + compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
> +
> + aliases {
> + ethernet0 = &gem0;
> + serial0 = &uart1;
> + spi0 = &qspi;
> + mmc0 = &sdhci0;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x4000>;
> + };
> +
> + chosen {
> + bootargs = "";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> +
> + ld4 {
> + label = "zynq-zybo-z7:green:ld4";
> + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + usb_phy0: phy0 {
> + #phy-cells = <0>;
> + compatible = "usb-nop-xceiv";
> + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&clkc {
> + ps-clk-frequency = <>;
> +};
> +
> +&gem0 {
> + status = "okay";
> + phy-mode = "rgmii-id";
> + phy-handle = <ðernet_phy>;
> +
> + ethernet_phy: ethernet-phy@0 {
> + reg = <0>;
> + device_type = "ethernet-phy";
> + };
> +};
> +
> +&qspi {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&sdhci0 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&uart1 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&usb0 {
> + status = "okay";
> + dr_mode = "host";
> + usb-phy = <&usb_phy0>;
> +};
> diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
> b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
> new file mode 100644
> index 00..f1b9357780
> --- /dev/null
> +++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
> @@ -0,0 +1,297 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
> + *
> + * Procedure to generate this file (using Vivado Webpack 2018.2):
> + * + Install board files from digilent/vivado-boards repository
> + * (commit 6a45981 from 2018-06-05)
> + * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
> + * + Create a block design
> + * - Add "ZYNQ7 Processing System" IP
> + * - Run "Block Automation" (Check "Apply Board Preset")
> + * - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
> + * - Save diagram changes
> + * - Go to sources view, select the block diagram,
> + * and select "Generate Output Products"
> + * + Copy the generated "ps7_init_gpl.c" file
> + * + Perform manu
[U-Boot] [PATCH v3] arm: zynq: add support for the zybo z7 board
The board is manufactured by Digilent
Main features:
- Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20)
- RAM: 1 GB DDR3L
- FLASH: 16 MB QSPI
- 1 Gbps Ethernet
- USB 2.0
- microSD slot
- Pcam camera connector
- HDMI Tx and Rx
- Audio codec: stereo out, stereo in, mic
- 5 (Z7-10) or 6 (Z7-20) Pmod ports
- 6 push-buttons, 4 switches, 5 LEDs
- 1 (Z7-10) or 2 (Z7-20) RGB LEDs
Signed-off-by: Luis Araneda
---
This patch adds support for the Digilent Zybo Z7 board
The only thing that I tested and is not working yet, is reading the
MAC address from the OTP region of the SPI flash memory, but I'm trying
to find a solution
Changes from v2:
- Removed silicon version 2_0 and 1_0 from ps7_init_gpl.c
Changes from v1:
- Rebased on u-boot/master
- Removed comments and indented ps7_init_gpl.c
- Removed CONFIG_DISPLAY from defconfig
- Replaced the cadence I2C driver by zynq_i2c
- Squashed the patches as they are less than 100kB now
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/zynq-zybo-z7.dts | 81 +
board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c | 297 ++
configs/zynq_zybo_z7_defconfig| 68
4 files changed, 448 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynq-zybo-z7.dts
create mode 100644 board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
create mode 100644 configs/zynq_zybo_z7_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 09adf5eab1..07d8729104 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -149,7 +149,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
- zynq-zybo.dtb
+ zynq-zybo.dtb \
+ zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts
new file mode 100644
index 00..3f8a3bfa0f
--- /dev/null
+++ b/arch/arm/dts/zynq-zybo-z7.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+#include
+
+/ {
+ model = "Digilent Zybo Z7 board";
+ compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x4000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ ld4 {
+ label = "zynq-zybo-z7:green:ld4";
+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ usb_phy0: phy0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
new file mode 100644
index 00..f1b9357780
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * Procedure to generate this file (using Vivado Webpack 2018.2):
+ * + Install board files from digilent/vivado-boards repository
+ * (commit 6a45981 from 2018-06-05)
+ * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
+ * + Create a block design
+ * - Add "ZYNQ7 Processing System" IP
+ * - Run "Block Automation" (Check "Apply Board Preset")
+ * - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
+ * - Save diagram changes
+ * - Go to sources view, select the block diagram,
+ * and select "Generate Output Products"
+ * + Copy the generated "ps7_init_gpl.c" file
+ * + Perform manual editions based on existing Zynq boards
+ * and the checkpatch.pl script
+ *
+ */
+
+#include
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0xF808, 0xDF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+ EMIT
