[U-Boot] CACHE: Misaligned operation
Hi, I just tested the current U-Boot master on my i.MX6Q board and the following two warnings showed up on the console: U-Boot 2016.09-rc1-00377-gb8698a2 CPU: Freescale i.MX6Q rev1.5 at 792 MHz Reset cause: POR DRAM: 1 GiB CACHE: Misaligned operation at range [4fff, 4fff0004] CACHE: Misaligned operation at range [4fff0024, 4fff0028] (But everything works fine, as far as I can tell for now) I did a git bisect and found out that these two warning messages are shown since commit 96e451bfa39b (arm: Show cache warnings in U-Boot proper only), where a debug statement was changed to a non-SPL warning. Was this intentional and is this warning something to be worried about? If not, we could add a new macro debug_non_spl with debug_cond !_SPL_BUILD && DEBUG and use that in check_cache_range. What do you think? Thanks, Clemens ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] CACHE: Misaligned operation
Hi, On 12 August 2016 at 08:13, Clemens Gruber wrote: > Hi, > > I just tested the current U-Boot master on my i.MX6Q board and the > following two warnings showed up on the console: > > U-Boot 2016.09-rc1-00377-gb8698a2 > > CPU: Freescale i.MX6Q rev1.5 at 792 MHz > Reset cause: POR > DRAM: 1 GiB > CACHE: Misaligned operation at range [4fff, 4fff0004] > CACHE: Misaligned operation at range [4fff0024, 4fff0028] > > (But everything works fine, as far as I can tell for now) > > I did a git bisect and found out that these two warning messages are > shown since commit 96e451bfa39b (arm: Show cache warnings in U-Boot > proper only), where a debug statement was changed to a non-SPL warning. > > Was this intentional and is this warning something to be worried about? Yes it means there is an error in the calling code. If you can figure out who is calling this then it is worth fixing. But also see recent discussions on the mailing list. Also possibly this patch? http://patchwork.ozlabs.org/patch/656474/ > > If not, we could add a new macro debug_non_spl with debug_cond > !_SPL_BUILD && DEBUG and use that in check_cache_range. > > What do you think? I'd rather fix the bugs :-) > > Thanks, > Clemens Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] CACHE: Misaligned operation
Hi Simon, > Hi, > > On 12 August 2016 at 08:13, Clemens Gruber > wrote: > > Hi, > > > > I just tested the current U-Boot master on my i.MX6Q board and the > > following two warnings showed up on the console: > > > > U-Boot 2016.09-rc1-00377-gb8698a2 > > > > CPU: Freescale i.MX6Q rev1.5 at 792 MHz > > Reset cause: POR > > DRAM: 1 GiB > > CACHE: Misaligned operation at range [4fff, 4fff0004] > > CACHE: Misaligned operation at range [4fff0024, 4fff0028] > > > > (But everything works fine, as far as I can tell for now) > > > > I did a git bisect and found out that these two warning messages are > > shown since commit 96e451bfa39b (arm: Show cache warnings in U-Boot > > proper only), where a debug statement was changed to a non-SPL > > warning. > > > > Was this intentional and is this warning something to be worried > > about? > > Yes it means there is an error in the calling code. If you can figure > out who is calling this then it is worth fixing. But also see recent > discussions on the mailing list. Also possibly this patch? > > http://patchwork.ozlabs.org/patch/656474/ Yes, this patch fixes the problem on iMX6. However, as I've pointed out here [1], there are other issues to be aware. [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg221577.html > > > > > If not, we could add a new macro debug_non_spl with debug_cond > > !_SPL_BUILD && DEBUG and use that in check_cache_range. > > > > What do you think? > > I'd rather fix the bugs :-) > > > > > Thanks, > > Clemens > > Regards, > Simon pgpYqo3P0BUKJ.pgp Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] CACHE: Misaligned operation
Hi, On Fri, Aug 12, 2016 at 09:27:29AM -0600, Simon Glass wrote: > Yes it means there is an error in the calling code. If you can figure > out who is calling this then it is worth fixing. But also see recent > discussions on the mailing list. Also possibly this patch? > > http://patchwork.ozlabs.org/patch/656474/ Thank you! Yes, this patch seems to fix the error. At least I can see no more warnings at boot. Will look into it more thoroughly next week and report back if there is still a problem. Regards, Clemens ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] CACHE: Misaligned operation for rpi_3_32b_defconfig
Hi Guys, I have just built a u-boot.bin for rpi_3_32b_defconfig using all the defaults. I then used this on the new Raspbian Buster image that was released a few days ago i.e. 2019-06-20-raspbian-buster-lite.zip. This same u-boot.bin works fine on the old Raspbian Stretch version ( 2019-04-08-raspbian-stretch.zip). Booting the RPI with Raspbian Buser gives the following error: U-Boot 2019.07-rc4-00287-g5eea874b5e-dirty (Jun 27 2019 - 22:00:42 +) DRAM: 948 MiB RPI 3 Model B (0xa02082) MMC: mmc@7e202000: 0, sdhci@7e30: 1 Loading Environment from FAT... *** Warning - bad CRC, using default environment mbox: Header response code invalid bcm2835: Could not configure display In:serial Out: vidconsole Err: vidconsole Net: CACHE: Misaligned operation at range [3b3da9e8, 3b3daa00] CACHE: Misaligned operation at range [3b3da9e8, 3b3daa00] CACHE: Misaligned operation at range [3b3da9e8, 3b3daa00] Any help would be greatly appreciated! Thanks for your time. Elliot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot